EP-4742243-A1 - PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Abstract

A package substrate a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the core including glass and a first recess in the first surface, a first bonding layer contacting the first surface of the core and filling the first recess, a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, a first insulation layer structure on the first bonding layer and partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a first portion of the first wiring structure.

Inventors

• PARK, OKGYEONG

Assignees

• Samsung Electronics Co., Ltd.

Dates

Publication Date

20260513

Application Date

20251027

Claims (13)

1. A package substrate comprising: a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a first portion of the first wiring structure.
2. The package substrate according to claim 1, wherein the first surface and the second surface are substantially flat.
3. The package substrate according to claim 1 or 2, wherein a width in the horizontal direction of the first recess is substantially constant in the vertical direction.
4. The package substrate according to claim 1 or 2, wherein a width in the horizontal direction of the first recess gradually decreases as a distance from the first surface of the core increases in the vertical direction.
5. The package substrate according to claim 1 or 2, wherein a width in the horizontal direction of the first recess gradually decreases and increases again as a distance from the first surface of the core increases in the vertical direction.
6. The package substrate according to any one of claims 1, 2 or 4, wherein a cross-section in the vertical direction of the first recess has a staircase shape.
7. The package substrate according to any one of claims 1 to 6, further comprising a plurality of first recesses that are spaced apart from each other in the horizontal direction, the first recess being one of the plurality of first recesses.
8. The package substrate according to any one of claims 1 to 7, wherein the first bonding layer includes epoxy, and the first insulation layer structure includes Ajinomoto build-up film.
9. The package substrate according to any one of claims 1 to 8, wherein the core further includes a second recess in the second surface of the core.
10. The package substrate according to claim 9, wherein the through electrode extends from the first surface, through the core, to the second surface in the vertical direction, and wherein the package substrate further comprises: a second bonding layer contacting the second surface of the core and filling the second recess; a second wiring structure on the second bonding layer and contacting the through electrode; a second insulation layer structure on the second bonding layer and at least partially covering the second wiring structure; and a second protective layer on the second insulation layer structure and covering a lower surface of a portion of the second wiring structure.
11. The package substrate according to claim 9 or 10, wherein the first recess and the second recess are arranged symmetrically with respect to a line passing through the core in the horizontal direction.
12. The package substrate of any one of claims 1 to 11, wherein: the first bonding layer comprises a first bonding sublayer and a second bonding sublayer, the first bonding sublayer is in the first recess, the first bonding sublayer including a first organic insulating material, and the second bonding sublayer contacts the first surface of the core and an upper surface of the first bonding sublayer, the second bonding sublayer including a second organic insulating material that is different from the first organic insulating material.
13. A semiconductor package comprising: a package substrate according to any one of the preceding claims; a semiconductor chip on the package substrate, the semiconductor chip including a conductive pad; a first conductive connection member contacting the conductive pad of the semiconductor chip, the conductive connection member being electrically connected to a second portion of the first wiring structure; and a molding member on the package substrate and covering the semiconductor chip and a sidewall of the first conductive connection member.

Description

BACKGROUND Example embodiments relate to a package substrate and a semiconductor package including the same. As an area of a package substrate increases, warpage occurs in the package substrate, and a method of increasing the stiffness of the core is needed. SUMMARY It is an aspect to provide a package substrate having enhanced electrical characteristics. It is another aspect to provide a semiconductor package having enhanced electrical characteristics. According to an aspect of one or more example embodiments, there is provided a package substrate comprising a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure. According another aspect of one or more example embodiments, there is provided a package substrate comprising a core including glass, the core having a first surface and a second surface opposite the first surface in a vertical direction and a first recess in the first surface; a first bonding layer in the first recess, the first bonding layer including a first organic insulating material; a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer including a second organic insulating material that is different from the first organic insulating material; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure. According to yet another aspect of one or more example embodiments, there is provided a semiconductor package comprising a package substrate including a core including glass and having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat and the core including a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a first portion of the first wiring structure; a semiconductor chip on the package substrate, the semiconductor chip including a conductive pad; a first conductive connection member contacting the conductive pad of the semiconductor chip, the conductive connection member being electrically connected to a second portion of the first wiring structure; and a molding member on the package substrate and covering the semiconductor chip and a sidewall of the first conductive connection member. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects will be more clear based on the following description in combination with the drawings, in which: FIG. 1 is a cross-sectional view illustrating a package substrate in accordance with example embodiments;FIGS. 2 to 6 are cross-sectional views illustrating a method of manufacturing a package substrate in accordance with example embodiments;FIG. 7 is a cross-sectional view illustrating a package substrate in accordance with example embodiments;FIGS. 8 to 10 are cross-sectional views illustrating package substrates in accordance with example embodiments;FIG. 11 is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments; andFIG. 12 is a cross-sectional view illustrating an electronic device in accordance with example embodiments. DETAILED DESCRIPTION Hereinafter,