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EP-4742245-A1 - ELECTRONIC DEVICE COMPRISING A MEMORY CIRCUIT

EP4742245A1EP 4742245 A1EP4742245 A1EP 4742245A1EP-4742245-A1

Abstract

The present description relates to a memory device (300) comprising a plurality of memory cells organized in a matrix of rows, words, and bits, each cell comprising a phase-change memory element (M) and two transistors (T), connected by their first nodes, themselves connected to a first terminal of the element, where: the elements of a bit line are connected by their second terminals; the two transistors of a word line are connected by their gates; Each cell is connected to two source lines, respectively connected to two second nodes of the transistors, with the cells of a word line being connected to both source lines and the cells of two successive word lines being connected to a common source line; and Each transistor is arranged in and on a pair of two fins arranged in a semiconductor substrate (301).

Inventors

  • WEBER, OLIVIER

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260513
Application Date
20251105

Claims (15)

  1. Memory device (200; 300; 400) comprising a plurality of memory cells (101) arranged in a matrix of word lines (WL) and bit lines (BL), each memory cell (101) comprising a memory element (M) made of a phase-change material (329) and two finned field-effect transistors (T) for selecting the memory element (M), each transistor (T) comprising first (D) and second (S) conduction nodes and a gate, the memory element (M) comprising two terminals, in which: - the two transistors of the same memory cell (101) are connected to each other by their first conduction nodes (D), said first conduction nodes (D) being themselves connected to a first terminal of the memory element (M); - the memory elements (M) of the same bit line (BL) are all connected to each other by their second terminals; - the two transistors (T) of the memory cells (101) of the same word line (WL) are all connected to each other, by their gates; - each memory cell (101) is connected to two source lines (SL), the two source lines (SL) being connected respectively to the two second conduction nodes (S) of the transistors (T) of the memory cell (101), the memory cells (101) of the same word line (WL) being connected to the same two source lines (SL) and the memory cells (101) of two successive word lines (WL) being connected to a common source line (SL); and - each transistor (T) is arranged in and on a pair of two parallel and adjacent fins arranged in a semiconductor substrate (301).
  2. Memory device according to claim 1, in which the transistors (T) of the memory cells of the same bit line (BL) are arranged in and on the same pair of two fins (A).
  3. Memory device according to claim 1 or 2, wherein the fins of the same pair are spaced 20 nm to 25 nm apart, for example about 22 nm.
  4. Memory device according to any one of claims 1 to 3, wherein the pairs of fins, on and in which are arranged the memory cells of two successive bit lines, are spaced from 60 nm to 65 nm, for example about 62 nm.
  5. Memory device according to any one of claims 1 to 4, wherein the phase-change material (329) is an alloy of germanium, antimony and tellurium.
  6. Memory device according to any one of claims 1 to 5, wherein, within each memory cell (101), the memory element (M) is separated from the transistors (T) by an interconnect stack (317).
  7. Memory device according to claim 6, wherein each memory element (M) is connected to the first conduction nodes (D) of the two transistors (T) of the same memory cell (M) via a conductor via (403) through the interconnect stack (317).
  8. Memory device according to any one of claims 1 to 7, wherein the memory element (M) comprises a heating metallic resistive element (331) disposed under the phase-change material (329) and controlling that same material.
  9. Memory device according to any one of claims 1 to 8, wherein the source lines (SL) are, in top view, parallel to the word lines (WL).
  10. Memory device according to any one of claims 1 to 9, wherein the fins of the same pair are closer together than fins (303) of two neighboring pairs.
  11. Memory device according to claim 10, wherein the fins are arranged in a first region (b) of the semiconductor substrate, the device further comprising other fins, regularly spaced, arranged in a second region (a) of the semiconductor substrate.
  12. A method for manufacturing a device comprising a plurality of memory cells (101) arranged in a matrix of word lines (WL) and bit lines (BL), each memory cell (101) comprising a memory element (M) made of a phase-change material (329) and two finned field-effect transistors (T) for selecting the memory element (M), each transistor (T) comprising first (D) and second (S) conduction nodes and a gate, the memory element (M) comprising two terminals (B1, B2), wherein: - the two transistors of the same memory cell (101) are connected to each other by their first conduction nodes (D), said first conduction nodes (D) being themselves connected to a first terminal (B1) of the memory element (M); - the memory elements (M) of the same bit line (BL) are all connected to each other by their second terminals; - the two transistors (T) of the memory cells (101) of a The same line of words (WL) are all connected to each other, by their grids; - each memory cell (101) is connected to two source lines (SL), the source lines (SL) being connected respectively to the two second conduction nodes (S) of the transistors (T) of the memory cell (101), the memory cells (101) of the same word line (WL) being connected to the same two source lines (SL) and the memory cells (101) of two successive word lines (WL) being connected to a common source line (SL), the process comprising the steps of: - formation of fins in a semiconductor substrate, the fins being formed in pairs; - formation of a semiconductor layer (307) by epitaxy; and - doping of the semiconductor layer (307) so as to form regions (309, 311) among which first regions (309) correspond to source regions and second regions (311) correspond to drain regions, a drain region being common to the two transistors of the same memory cell and a source region being common to two transistors of two neighboring memory cells (101).
  13. A method according to claim 12, wherein the fins of the same pair are closer together than the fins (303) of two neighboring pairs.
  14. A method according to claim 13, wherein the fin formation is carried out in a first region (b) of the semiconductor substrate, the process further comprising, during the fin formation stage, the formation of other fins, regularly spaced, in a second region (a) of the semiconductor substrate.
  15. Method of using the device according to any one of claims 1 to 11, comprising for the selection of a memory cell (101) of a first line of words (WL) and a first line of bits (BL): - application of a first non-zero potential on the first bit line (BL) and a zero potential on the other bit lines (BL); - application of a second non-zero potential on the first word line (WL) and a zero potential on the other word lines (WL); - application of a zero potential to the two source lines (SL) connected to the memory cells of the first word line and a third non-zero potential to the other source lines (SL).

Description

technical field This description relates generally to electronic devices and more specifically to electronic devices including a memory circuit. Previous technique Electronic devices include both memory circuits and logic circuits. This discussion focuses specifically on electronic devices comprising memory circuits, known as memory devices, which include memory elements arranged in a matrix. Each memory element is associated with one or more selector transistors. These transistors are used to program, erase, or read each memory element independently. It would be desirable to improve at least some aspects of known electronic devices. Summary of the invention To this end, one embodiment provides a memory device comprising a plurality of memory cells arranged in a matrix of word rows and bit rows, each memory cell comprising a memory element made of a phase-change material and two finned field-effect transistors for selecting the memory element, each transistor comprising first and second conduction nodes and a gate, the memory element comprising two terminals, in which: the two transistors of the same memory cell are connected to each other by their first conduction nodes, said first conduction nodes being themselves connected to a first terminal of the memory element; The memory elements of the same bit line are all connected to each other by their second terminals; the two transistors of the memory cells of the same word line are all connected to each other, by their gates; Each memory cell is connected to two source lines, the two source lines being connected respectively to the two second conduction nodes of the memory cell's transistors, the memory cells of the same word line being connected to the same two source lines, and the memory cells of two successive word lines being connected to a common source line; and Each transistor is arranged in and on a pair of two parallel and adjacent fins arranged in a semiconductor substrate. According to one embodiment, the transistors of the memory cells of the same bit line are arranged in and on the same pair of two fins. According to one embodiment, the fins of the same pair are spaced 20 nm to 25 nm apart, for example about 22 nm. According to one embodiment, the pairs of fins, on and in which the memory cells of two successive bit lines are arranged, are spaced 60 nm to 65 nm apart, for example about 62 nm. According to one embodiment, the phase change material is an alloy of germanium, antimony and tellurium. According to one embodiment, within each memory cell, the memory element is separated from the transistors by an interconnect stack. According to one embodiment, each memory element is connected to the first conduction nodes of the two transistors of the same memory cell via a conductor passing through the interconnect stack. According to one embodiment, the memory element comprises a heating metallic resistive element disposed under the phase change material and controlling that same material. According to one embodiment, the source lines are, in top view, parallel to the word lines. According to one embodiment, the fins are arranged in a first region of the semiconductor substrate, the device further comprising other fins, regularly spaced, arranged in a second region of the semiconductor substrate. Another embodiment provides a method for manufacturing a device comprising a plurality of memory cells arranged in a matrix of word rows and bit rows, each memory cell comprising a memory element made of a phase-change material and two finned field-effect transistors for selecting the memory element, each transistor comprising first and second (S) conduction nodes and a gate, the memory element having two terminals, wherein: the two transistors of the same memory cell are connected to each other by their first conduction nodes, said first conduction nodes being themselves connected to a first terminal of the memory element; The memory elements of the same bit line are all connected to each other by their second terminals; the two transistors of the memory cells of the same word line are all connected to each other, by their gates; Each memory cell is connected to two source lines, the source lines being connected respectively to the two second conduction nodes of the memory cell transistors, the memory cells of the same word line being connected to the same two source lines and the memory cells of two successive word lines being connected to a common source line, the process comprising the steps of: fin formation in a semiconductor substrate, the fins being formed in pairs; formation of a semiconductor layer by epitaxy; and doping of the semiconductor layer so as to form regions among which first regions correspond to source regions and second regions correspond to drain regions, a drain region being common to the two transistors of the same memory cell and a source region being common to two transistors of two neighboring memory cells. According to one