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EP-4742246-A1 - ELECTRONIC CHIP COMPRISING A MEMORY CIRCUIT

EP4742246A1EP 4742246 A1EP4742246 A1EP 4742246A1EP-4742246-A1

Abstract

This description relates to an electronic chip comprising a memory circuit including: an interconnection stack; several memory cells, each comprising a memory element (108) above the stack and a fine-FET comprising a first node and formed in the substrate, Each element comprises a first electrode, a layer (114) comprising an OTS material, and a second electrode (116) connected to the layer on the side opposite the first electrode, In each cell, the first node of the transistor is connected to the element via a conductor (138) passing through the entire thickness of the stack, The memory circuit includes a control circuit configured to apply, between the first and second electrodes of each element, a first or second voltage pulse of respectively a first or second polarity, opposite to the first polarity, to define respectively a first or a second logical state of the element.

Inventors

  • REDAELLI, ANDREA
  • ANNUNZIATA, ROBERTO

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260513
Application Date
20251105

Claims (15)

  1. Electronic chip (300) comprising a memory circuit (100) comprising: - a semiconductor substrate (102); - an interconnect stack (104), arranged on the semiconductor substrate (102); and - a plurality of memory cells (106), each memory cell (106) comprising a memory element (108) arranged above the interconnect stack (104) and a selection transistor (110) comprising a first conduction node and formed in the semiconductor substrate (102), in which each memory element (108) comprises a first electrode (112), an intermediate layer (114) comprising an ovoid threshold switching material, and a second electrode (116) connected to the intermediate layer (114) on the opposite side to the first electrode (112), in which, in each memory cell (106), the first conduction node of the selection transistor (110) is connected to the memory element (108) via a respective conductor (138) traversing the entire thickness of the interconnect stack (104), and in which the memory circuit (100) further comprises a control circuit (305) structured and configured to apply, between the first electrode (112) and the second electrode (116) of each memory element (108), a first voltage pulse of a first polarity to define a first logic state of the memory element (108) and a second voltage pulse of a second polarity, opposite to the first polarity, to define a second logic state of the memory element (108).
  2. Electronic chip (300) according to claim 1, wherein the selection transistor (110) is a finned field-effect transistor.
  3. Electronic chip (300) according to claim 1 or 2, wherein the intermediate layer (114) is made of a chalcogenide material and wherein the second electrode (116) comprises a resistor in electrical contact with the intermediate layer (114).
  4. Electronic chip (300) according to any one of claims 1 to 3, wherein the memory cells (106) are arranged in a matrix of bit lines (301) and word lines (303) and wherein each memory cell (106) is connected to a respective bit line (301) by its first electrode (112) and to a respective word line (303) by its second electrode (116) and wherein each transistor (110) comprises a gate which is connected to a respective word line (305), and a second conduction node connected to ground.
  5. Electronic chip (300) according to any one of claims 1 to 4, wherein the memory cells (106) are devoid of any phase-change material.
  6. Electronic chip (300) according to any one of claims 1 to 5, wherein the conductor via (138) is made of a metallic material.
  7. Electronic chip (300) according to any one of claims 1 to 6, wherein the interconnect stack (104) has a thickness in the range of 100 nm to 600 nm.
  8. Electronic chip (300) according to any one of claims 1 to 7, wherein the interconnect stack (104) comprises a plurality of levels, each level comprising a first insulating layer (118) and a second insulating layer (120), in which the first insulating layer (118) is made of a material selected from the group: SiOC, porous SiOC, SiOCH, or porous SiOCH, and has a thickness in the range of 30 nm to 110 nm, and in which the second insulating layer (120) is made of a material selected from the group: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN, and has a thickness in the range of 2 nm to 50 nm.
  9. Electronic chip (300) according to any one of claims 1 to 8, comprising: a third insulating layer (124) interposed between the interconnect stack (104) and the memory element (108), wherein the third insulating layer (124) is made of a material selected from the group: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and has a thickness in the range of 2 nm to 50 nm; and a fourth insulating layer (126) interposed between the third insulating layer (124) and the memory element (108), and wherein the fourth insulating layer (126) is made of SiO2 , and has a thickness in the range of 10 nm to 50 nm.
  10. Electronic chip (300) according to any one of claims 1 to 9, wherein, for each memory element (108), the respective conductor via (138) is of one piece.
  11. Electronic chip (300) according to any one of claims 1 to 10, further comprising: an additional insulating layer (124) interposed between the semiconductor substrate (102) and the interconnect stack (104), and for each memory element (108), another respective via (140) passing through the entire thickness of the additional insulating layer (124) and directly connecting the selection transistor (110) to the respective conductor via (138).
  12. Electronic chip (300) according to any one of claims 1 to 11, wherein the via conductor (138) is connected directly to the second electrode (116) of the memory element (108).
  13. A method for manufacturing an electronic chip (300) comprising a memory circuit (100), comprising the following successive steps: a) the formation of selection transistors (110), comprising a first conduction node, in a semiconductor substrate (102); b) the formation of an interconnect stack (104), arranged on the semiconductor substrate (102); and c) the formation of a plurality of memory elements (108) arranged above the interconnect stack (104), each memory element (108) comprising a first electrode (112), an intermediate layer (114) comprising an ovoid threshold switching material, and a second electrode (116) connected to the intermediate layer (114) on the opposite side with respect to the first electrode, the first conduction node of the selection transistor (110) of each memory cell (106) being connected to the memory element (108) via a respective conductor (138) passing through the entire thickness of the interconnection stack (104), the method further comprising a step of forming a control circuit (305) structured and configured to apply, between the first electrode (112) and the second electrode (116) of each memory element (108), a first voltage pulse of a first polarity to define a first logic state of the memory element (108) and a second voltage pulse of a second polarity, opposite to the first polarity, to define a second logic state of the memory element (108).
  14. Method according to claim 13, wherein the conductive via (138) is formed between steps b) and c).
  15. Method according to claim 14, wherein the step of forming the conductive vias (138) includes a step of etching the interconnect stack (104) so as to form openings and a step of filling said openings.

Description

technical field This description relates generally to electronic chips and more particularly to electronic chips comprising a memory circuit based on an ovonic threshold switching (OTS) material. Previous technique Electronic chips contain both memory circuits and logic circuits. This discussion focuses specifically on electronic chips with memory circuits, comprising memory elements arranged in a matrix, each memory element being associated with one or more selector transistors. These transistors are used to program, erase, or read each memory element individually. An OTS material switches from the "on" state to the "off" state depending on the voltage applied to the electronic cell. The state of the oval threshold switch changes when the voltage across it exceeds a threshold voltage. When the threshold voltage is reached, the "on" state is triggered, and the oval threshold switch is in a substantially conductive state. If the current or voltage potential falls below the threshold value, the oval threshold switch returns to the "off" state. It would be desirable to improve at least some aspects of known electronic chips. Summary of the invention To achieve this, one embodiment provides for an electronic chip comprising a memory circuit including: a semiconductor substrate; an interconnect stack, arranged on the semiconductor substrate; and a plurality of memory cells, each memory cell comprising a memory element arranged above the interconnect stack and a finned field-effect selector transistor comprising a first conduction node and formed in the semiconductor substrate, in which each memory element comprises a first electrode, an intermediate layer comprising an oval threshold switching material, and a second electrode connected to the intermediate layer on the side opposite the first electrode, in which, in each memory cell, the first conduction node of the selection transistor is connected to the memory element via a respective conductor through the entire thickness of the interconnect stack, and in which the memory circuit further comprises a control circuit structured and configured to apply, between the first electrode and the second electrode of each memory element, a first voltage pulse of a first polarity to define a first logic state of the memory element and a second voltage pulse of a second polarity, opposite to the first polarity, to define a second logic state of the memory element. According to one embodiment, the intermediate layer is made of a chalcogenide material and the second electrode comprises a resistor in electrical contact with the intermediate layer. According to one embodiment, the memory cells are organized into a matrix of bit rows and word rows, and each memory cell is connected to a row of respective bits by its first electrode and to a respective line of words by its second electrode. According to one embodiment, each transistor comprises a gate which is connected to a respective word line, and a second conduction node connected to ground. According to one embodiment, the memory cells are devoid of any phase-change material. According to one embodiment, the conductive via is made of a metallic material. According to one embodiment, the interconnect stack has a thickness in the range of 100 nm to 600 nm. According to one embodiment, the interconnection stack comprises a plurality of levels, each level comprising a first insulating layer and a second insulating layer, the first insulating layer is made of a material chosen from the group: SiOC, porous SiOC, SiOCH, or porous SiOCH, and has a thickness in the range of 30 nm to 110 nm, and the second insulating layer is made of a material chosen from the group: silicon carbonitride, silicon nitride, SiCH, SiNHC or porous SiCN, and has a thickness in the range of 2 nm to 50 nm. In one embodiment, the electronic chip comprises: a third insulating layer interposed between the interconnect stack and the memory element, the third insulating layer being made of a material chosen from the group: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and having a thickness within the range ranging from 2 nm to 50 nm; and a fourth insulating layer interposed between the third insulating layer and the memory element, the fourth insulating layer being made of SiO2 and having a thickness in the range of 10 nm to 50 nm. According to one embodiment, for each memory element, the respective conductor via is a single piece. According to one embodiment, the electronic chip comprises: an additional insulating layer interposed between the semiconductor substrate and the interconnect stack, and, for each memory element, a respective additional via traversing the entire thickness of the additional insulating layer and directly connecting the select transistor to the respective conductive via. According to one embodiment, the conductor via is connected directly to the second electrode of the memory element. Another embodiment provides