EP-4742247-A1 - MEMORY ARCHITECTURES WITH AMBIPOLAR SEMICONDUCTOR CHANNELS

Abstract

Methods, systems, and devices for memory architectures with ambipolar semiconductor channels are described. A memory device may include multiple conductors that are each associated with a respective activation line of a memory array, and a pillar that extends through the conductors. The pillar may include a semiconductor material extending along a length of the pillar and associated with an ambipolar channel along the length of the pillar. The memory device may also include multiple storage portions each including one or more storage materials (e.g., to store a charge, a dipole polarization, or a combination thereof). Each storage portion may be associated with a respective memory cell of the memory array and may be positioned between a respective one of the conductors and a respective portion of the semiconductor material along the length of the pillar.

Inventors

• FANTINI, PAOLO
• TORTORELLI, INNOCENZO
• PIROVANO, AGOSTINO
• FARRONATO, Matteo
• IELMINI, DANIELE

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260513

Application Date

20251112

Claims (15)

1. A memory device, comprising: a plurality of conductors distributed along a direction from a substrate of the memory device, each of the plurality of conductors associated with a respective one of a plurality of activation lines of a memory array; a pillar extending along the direction from the substrate and through the plurality of conductors, the pillar comprising a semiconductor material extending along a length of the pillar and associated with an ambipolar channel along the length of the pillar; and a plurality of storage portions, each of the plurality of storage portions associated with a respective memory cell of the memory array and comprising one or more storage materials positioned between a respective one of the plurality of conductors and a respective portion of the semiconductor material along the length of the pillar.
2. The memory device of claim 1, wherein a conductivity of the ambipolar channel is above a threshold conductivity in response to activation voltages below a first threshold voltage, below the threshold conductivity in response to activation voltages between the first threshold voltage and a second threshold voltage, and above the threshold conductivity in response to activation voltages above the second threshold voltage.
3. The memory device of claim 1, wherein the semiconductor material comprises a transition metal dichalcogenide material.
4. The memory device of claim 1, wherein each of the plurality of storage portions comprises a ferroelectric material, a charge-trapping material, or a combination thereof.
5. The memory device of claim 4, wherein each respective memory cell is operable to store a respective logic state based at least in part on a charge stored in a respective portion of the charge-trapping material of the one or more storage materials, on a dipole polarization stored in a respective portion of the ferroelectric material of the one or more storage materials, or a combination thereof.
6. The memory device of claim 1, wherein the one or more storage materials are included in a continuous formation of the one or more storage materials around the semiconductor material.
7. The memory device of claim 1, wherein the semiconductor material is a layer of semiconductor material around a dielectric core of the pillar.
8. The memory device of claim 1, wherein, for each of the plurality of storage portions, a storage material of the one or more storage materials is in contact with a respective portion of the semiconductor material.
9. The memory device of claim 1, further comprising: one or more dielectric materials positioned between the plurality of conductors and the plurality of storage portions.
10. The memory device of claim 1, further comprising: a first select line operable to couple a first end of the pillar with a first access line of the memory array; and a second select line operable to couple a second end of the pillar with a second access line of the memory array.
11. A method for operating a memory device, comprising: writing a logic state to a memory cell of a memory array, wherein the writing comprises: biasing a pillar with a first voltage, the pillar associated with an ambipolar semiconductor channel extending along a length of the pillar through a plurality of activation lines of the memory array; biasing a first activation line of the plurality of activation lines with a second voltage that is less than the first voltage, the first activation line coupled with the memory cell; biasing one or more second activation lines of the plurality of activation lines, other than the first activation line, with a third voltage that is different than the first voltage and the second voltage; and storing an electric field in one or more storage materials based at least in part on biasing the pillar with the first voltage, biasing the first activation line with the second voltage, and biasing the one or more second activation lines with the third voltage, the one or more storage materials being positioned between the first activation line and the ambipolar semiconductor channel.
12. The method of claim 11, wherein: biasing the first activation line with the second voltage that is less than the first voltage is configured to activate a first portion of the ambipolar semiconductor channel; and biasing the one or more second activation lines with the third voltage that is different than the first voltage and the second voltage is configured to activate one or more second portions of the ambipolar semiconductor channel.
13. The method of claim 11, wherein an absolute difference between the second voltage and the first voltage is greater than an absolute difference between the third voltage and the first voltage.
14. The method of claim 11, wherein the third voltage is between the first voltage and the second voltage.
15. The method of claim 11, wherein biasing the pillar with the first voltage is based at least in part on coupling the pillar with an access line of the memory array that is biased with the first voltage.

Description

TECHNICAL FIELD The following relates to one or more systems for memory, including memory architectures with ambipolar semiconductor channels. BACKGROUND Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross point), not-or (NOR) and not-and (NAND) memory devices, and others. Memory devices may be described in terms of volatile configurations or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed states over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND) may maintain their programmed states for extended periods of time even in the absence of an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of a memory system that supports memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein.FIG. 2 shows an example of a memory architecture that supports memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein.FIG. 3 shows an example of an architecture that supports memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein.FIGs. 4A and 4B show examples of operations on an architecture that supports memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein.FIG. 5 shows a block diagram of a memory device that supports memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein.FIG. 6 shows a flowchart illustrating a method or methods that support memory architectures with ambipolar semiconductor channels in accordance with examples as disclosed herein. DETAILED DESCRIPTION Some memory systems may be expected to support data-intensive applications, such as artificial intelligence (AI) applications and other processes associated with a relatively large quantity of access operations. Such applications may be associated with relatively high-speed data access and may utilize substantial portions of a memory device. However, some memory devices (e.g., dynamic random access memory (DRAM), central processing unit (CPU) memory) may be constrained with relatively limited storage capacity and bandwidth capabilities, which may be inadequate for handling extensive data volumes. Further, other memory devices (e.g., solid state drive (SSD) memory devices, hard disk drive (HDD) memory devices) may support relatively higher storage capacity but may be associated with relatively high latency, which may impede performance in applications associated with increased data processing speeds. In some cases, capacity enhancements by reducing component size or pitch (e.g., along one or more dimensions of a memory array) may be limited (e.g., may become unfeasible or otherwise ineffective) based on practical and physical limitations of such techniques. In accordance with one or more techniques described herein, a memory system (e.g., a not-and (NAND) memory system, a ferroelectric NAND (FeNAND) system) may support an architecture that includes ambipolar channels (e.g., ambipolar semiconductor channels, pillar channels) of a semiconductor material, such as a transition metal dichalcogenide (TMD). The ambipolar feature of such a channel may refer to a capability of a material to support the generation (e.g., mobilization, conduction) of both electrons (e.g., negative charge, charge reduction, increase of electrons) and holes (e.g., positive charge, charge increase, reduction of electrons) at a same or relatively similar rate (e.g., an ability for the material to behave as both an n-type semiconductor and a p-type semiconductor). In some examples, the use of such semiconductor materials may enable a relatively efficient