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EP-4742302-A1 - SEMICONDUCTOR DEVICE

EP4742302A1EP 4742302 A1EP4742302 A1EP 4742302A1EP-4742302-A1

Abstract

A semiconductor device includes a semiconductor element (30L), a clip (50L) which is a metal plate, and a solder (81). The semiconductor element (30L) has a source electrode (32), a gate wiring (36) which is a signal line, and an insulating film (35). The gate wiring (36) is disposed at a position overlapping with an element region on one surface of a semiconductor substrate (34) and different from the source electrode (32). An upper element portion (354) of the insulating film (35) covers the gate wiring (36) and is interposed by the source electrode (32) in a plan view. The clip (50L) has a joint portion (51) to the source electrode (32). The solder (81) is interposed between the source electrode (32) and the joint portion (51). The joint portion (51) is disposed to avoid the gate wiring (36).

Inventors

  • HIRANO, TAKAHIRO
  • KAMIYA, MASAYUKI

Assignees

  • DENSO CORPORATION

Dates

Publication Date
20260513
Application Date
20240606

Claims (12)

  1. A semiconductor device comprising: at least one semiconductor element (30) that includes a semiconductor substrate (34) having an element region (341), a main electrode (32) disposed at a position overlapping with the element region on one surface of the semiconductor substrate, a signal line (36) disposed at a position overlapping with the element region on the one surface and being different from the position of the main electrode, and an insulating film (354, 35) covering the signal line and interposed by the main electrode in a plan view in a thickness direction of the semiconductor substrate; a metal plate (50, 50H, 50L) having a joint portion (51) to the main electrode; and a solder (81) interposed between the main electrode and the joint portion and joining the main electrode and the metal plate, wherein the joint portion is disposed to avoid the signal line.
  2. The semiconductor device according to claim 1, wherein the metal plate has a plurality of the joint portions for a same semiconductor element.
  3. The semiconductor device according to claim 2, wherein the joint portions for the same semiconductor element are branched.
  4. The semiconductor device according to claim 3, wherein the metal plate has a bridge portion (56) connected to the joint portions that are adjacent to each other at a position farther away from the one surface than the joint portions.
  5. The semiconductor device according to any one of claims 1 to 4, wherein the metal plate has a plurality of first joint portions as the joint portion, and a second joint portion (52) which is different from the first joint portions.
  6. The semiconductor device according to claim 5, further comprising: a substrate (40) having an insulating base material (41) and a wiring (422, 423) disposed at the insulating base material, wherein the semiconductor element is disposed on a surface of the substrate on which the wiring is disposed, and the second joint portion is connected to the wiring.
  7. The semiconductor device according to claim 5, wherein the semiconductor element includes a first main electrode as the main electrode, and a second main electrode (31) disposed on a rear surface of the semiconductor substrate opposite to the one surface, and the semiconductor device further comprising: a metal member (421, 423); and a sintered member (82) interposed between the second main electrode and the metal member and joining the second main electrode and the metal member.
  8. The semiconductor device according to claim 5, wherein the semiconductor element has a pad (33) disposed on the one surface and electrically connected to the signal line, the semiconductor device further comprising: a signal terminal (62); a bonding wire (80) electrically connecting the pad and the signal terminal; and a gel (91) that seals the semiconductor element, the metal plate, a part of the signal terminal, and the bonding wire, wherein the metal plate is formed with a through hole (55) at a portion connecting the plurality of first joint portions and the second joint portion.
  9. The semiconductor device according to claim 5, further comprising: a sealing body (90) that seals the semiconductor element and the metal plate, wherein the metal plate has an inclined shape at a portion connecting the plurality of first joint portions and the second joint portion, the inclined shape being inclined with respect to a direction in which the plurality of first joint portions and the second joint portion are aligned.
  10. The semiconductor device according to claim 5, wherein the semiconductor element includes a plurality of the semiconductor elements, one of the plurality of first joint portions is joined to one of the plurality of semiconductor elements, and another of the plurality of first joint portions is joined to another of the plurality of semiconductor elements.
  11. The semiconductor device according to claim 10, wherein the metal plate has a coupling portion (53) connecting the plurality of first joint portions and the second joint portion, and the coupling portion has a shape that branches from the second joint portion to the plurality of first joint portions and branches to avoid a region between the plurality of semiconductor elements.
  12. The semiconductor device according to claim 10, wherein the metal plate has a coupling portion (57) connecting the plurality of first joint portions and the second joint portion, and the coupling portion has a shape that branches from the second joint portion to the plurality of first joint portions and branches from a region between the plurality of semiconductor elements.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based on and claims the benefit of priority from Japanese Patent Application No. 2023-110768 filed on July 5, 2023 and Japanese Patent Application No. 2024-070077 filed on April 23, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND ART Patent Literature 1 discloses a semiconductor device including a semiconductor element and a metal plate which is soldered and joined to a main electrode of the semiconductor element. Contents of the description of the prior art literature are incorporated herein by reference as a description of technical elements in this description. PRIOR ART LITERATURE PATENT LITERATURE Patent Literature 1: JP 2022-130702 A SUMMARY OF INVENTION As disclosed in Patent Literature 1, a signal line such as a gate liner can be disposed on an element region of a semiconductor substrate. The signal line is covered with an insulating film, and is insulated and separated from the main electrode. In the configuration of Patent Literature 1, there is a risk that solder may flow into a scratch or the like in the insulating film, causing leakage in the signal line, for example, gate leakage. In the above viewpoint and in other viewpoints not mentioned, further improvements are required for the semiconductor device. An object of the disclosure is to provide a semiconductor device capable of suppressing leakage in a signal line. According to an aspect of the disclosure, there is provided a semiconductor device including: at least one semiconductor element that includes a semiconductor substrate having an element region, a main electrode disposed at a position overlapping with the element region on one surface of the semiconductor substrate, a signal line disposed at a position overlapping with the element region on the one surface and being different from the position of the main electrode, and an insulating film covering the signal line and interposed by the main electrode in a plan view in a thickness direction of the semiconductor substrate; a metal plate having a joint portion to the main electrode; and a solder interposed between the main electrode and the joint portion and joining the main electrode and the metal plate, in which the joint portion is disposed to avoid the signal line. With the disclosed semiconductor device, the joint portion of the metal plate is disposed to avoid the signal line. Therefore, it is possible to suppress the solder from flowing into a scratch in the insulating film covering the signal line. Therefore, leakage in the signal line can be suppressed. A plurality of aspects disclosed in the description adopt different technical means to achieve respective objects. Reference numerals in parentheses in the claims and items exemplify the correspondence with portions of embodiments described later, and are not intended to limit the technical scope. Objects, features, and advantageous effects disclosed in this description will become more apparent with reference to the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied.FIG. 2 is a perspective view illustrating an example of a semiconductor module.FIG. 3 is a plan view of the semiconductor module.FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3.FIG. 5 is a plan view illustrating an example of the semiconductor device.FIG. 6 is a plan view illustrating a wiring pattern of a substrate.FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5.FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate.FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate.FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate.FIG. 11 is a circuit diagram illustrating a verification model.FIG. 12 is a diagram illustrating a verification result.FIG. 13 is a diagram illustrating a temperature distribution.FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit.FIG. 15 is a plan view illustrating a modification example.FIG. 16 is a plan view illustrating another modification example.FIG. 17 is a plan view illustrating still another modification example.FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment.FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18.FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module.FIG. 21 is a plan view illustrating an example of a connecti