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EP-4742530-A1 - AMPLIFIER AND OPERATION METHOD THEREOF

EP4742530A1EP 4742530 A1EP4742530 A1EP 4742530A1EP-4742530-A1

Abstract

An amplifier (100) includes a signal input terminal (NIN), a signal output terminal (NOUT), an amplification circuit (101), and at least one variable voltage generation circuit (110). The signal input terminal (NIN) may receive an input signal (SIN). The signal output terminal (NOUT) may output an amplified signal (SOUT). A transistor (T1) of the amplification circuit (101) includes a first terminal, a second terminal, a control terminal, and a body terminal, where the control terminal is coupled to the signal input terminal (NIN), the second terminal is coupled to the signal output terminal (NOUT), and the body terminal is floating. The variable voltage generation circuit (110) is coupled to the transistor (T1). During a transition period, a first voltage difference presents between the second and first terminals of the transistor (T1), and during a steady period, a second voltage difference smaller than the first voltage difference presents.

Inventors

  • PENG, TIEN-YUN
  • CHEN, CHIH-SHENG

Assignees

  • RichWave Technology Corp.

Dates

Publication Date
20260513
Application Date
20251102

Claims (15)

  1. An amplifier (100, 200, 500, 600, 800, 900), characterised by comprising: a signal input terminal (NIN) configured to receive an input signal (SIN); a signal output terminal (NOUT) configured to output an amplified signal (SOUT); an amplification circuit (101, 201, 501, 601, 801, 901) coupled between the signal input terminal (NIN) and the signal output terminal (NOUT), the amplification circuit (101, 201, 501, 601, 801, 901) comprising a first transistor (T1), the first transistor (T1) comprising a first terminal, a second terminal, a control terminal and a body terminal, wherein the first terminal of the first transistor (T1) is coupled to a first node (N1), the second terminal of the first transistor (T1) is coupled to a second node (N2), the control terminal of the first transistor (T1) is coupled to the signal input terminal (NIN), and the body terminal of the first transistor (T1) is floating; and at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) coupled to the amplification circuit (101, 201, 501, 601, 801, 901); wherein: during a transition period (PT), the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) provides a first voltage difference (VDS1) between the second terminal and the first terminal of the first transistor (T1); and during a steady period (PS), the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) provides a second voltage difference (VDS2) between the second terminal and the first terminal of the first transistor (T1); and the first voltage difference (VDS1) is greater than the second voltage difference (VDS2).
  2. The amplifier (200, 500, 600, 800, 900) of claim 1, characterised in that : the amplification circuit (201, 501, 601, 801, 901) further comprises: a second transistor (T2), comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor (T2) is coupled to the second node (N2), the second terminal of the second transistor (T2) is coupled to the signal output terminal (NOUT), and the control terminal of the second transistor (T2) is coupled to a third node (N3).
  3. The amplifier (200) of claim 2, characterised in that : the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) comprises a first variable voltage generation circuit (210) coupled to the third node (N3) and configured to provide a first pulse voltage signal (VPS1) at the third node (N3); during the transition period (PT), the first pulse voltage signal (VPS1) has a first voltage level (L1); and during the steady period (PS), the first pulse voltage signal (VPS1) has a second voltage level (L2); or the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) comprises a second variable voltage generation circuit (520, 620) coupled to the second node (N2) and configured to provide a second pulse voltage signal (VPS2) at the second node (N2); during the transition period (PT), the second pulse voltage signal (VPS2) has a third voltage level (L3); and during the steady period (PS), the second pulse voltage signal (VPS2) has a fourth voltage level (L4); or the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) comprises a third variable voltage generation circuit (830, 930) coupled to the first node (N1) and configured to provide a third pulse voltage signal (VPS3) at the first node (N1); during the transition period (PT), the third pulse voltage signal (VPS3) has a fifth voltage level (L5); and during the steady period (PS), the third pulse voltage signal (VPS3) has a sixth voltage level (L6).
  4. The amplifier (200) of claim 3, characterised in that : during the transition period (PT), a voltage level (V2) at the second terminal of the first transistor (T1) is determined by the first voltage level (L1) of the first pulse voltage signal (VPS1); during the steady period (PS), the voltage level (V2) at the second terminal of the first transistor (T1) is determined by the second voltage level (L2) of the first pulse voltage signal (VPS1); and during both the transition period (PT) and the steady period (PS), a voltage level (V1) at the first terminal of the first transistor (T1) remains substantially unchanged.
  5. The amplifier (200) of claim 3, characterised in that : the first voltage level (L1) is different from the second voltage level (L2).
  6. The amplifier (200, 500, 600, 800, 900) of claim 2, characterised in that the second transistor (T2) further comprises a body terminal, and the body terminal of the second transistor (T2) is floating or contacted.
  7. The amplifier (200, 500, 600, 800, 900) of claim 2, characterised in that : the second terminal of the second transistor (T2) is further coupled to an operation voltage terminal (VDD); during the transition period (PT), the operation voltage terminal (VDD) provides a first operation voltage; during the steady period (PS), the operation voltage terminal (VDD) provides a second operation voltage; and the first operation voltage is higher than the second operation voltage.
  8. The amplifier (500, 600) of claim 3, characterised in that : the third voltage level (L3) is higher than the fourth voltage level (L4).
  9. The amplifier (600) of claim 3, characterised in that : the second variable voltage generation circuit (620) comprises a first switch (SW1), and the first switch (SW1) comprises a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch (SW1) is configured to receive a first reference voltage (VREF1), the second terminal of the first switch (SW1) is coupled to the second node (N2), and the control terminal of the first switch (SW1) is configured to receive a first control signal (VCTRL1); wherein: during the transition period (PT), the first switch (SW1) is turned on according to the first control signal (VCTRL1) such that the first reference voltage (VREF1) is received at the second node (N2); and during the steady period (PS), the first switch (SW1) is turned off according to the first control signal (VCTRL1).
  10. The amplifier (800, 900) of claim 3, characterised in that : the fifth voltage level (L5) is lower than the sixth voltage level (L6).
  11. The amplifier (900) of claim 3, characterised in that : the third variable voltage generation circuit (930) comprises a second switch (SW2), the second switch (SW2) comprises a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch (SW2) is coupled to the first node (N1), the second terminal of the second switch (SW2) is coupled to a second reference voltage terminal (VREF2), and the control terminal of the second switch (SW2) is configured to receive a second control signal (VCTRL2); the third variable voltage generation circuit (930) comprises a third switch (SW3), the third switch (SW3) comprises a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch (SW3) is coupled to the first node (N1), the second terminal of the third switch (SW3) is coupled to a third reference voltage terminal (VREF3), and the control terminal of the third switch (SW3) is configured to receive a third control signal (VCTRL3); a voltage level at the second reference voltage terminal (VREF2) is lower than a voltage level at the third reference voltage terminal (VREF3); during the transition period (PT), the second switch (SW2) is turned on according to the second control signal (VCTRL2), and the third switch (SW3) is turned off according to the third control signal (VCTRL3), such that a voltage provided by the second reference voltage terminal (VREF2) is received at the first node (N1); and during the steady period (PS), the second switch (SW2) is turned off according to the second control signal (VCTRL2), and the third switch (SW3) is turned on according to the third control signal (VCTRL3) such that a voltage provided by the third reference voltage terminal (VREF3) is received at the first node (N1).
  12. The amplifier (100, 200, 500, 600, 800, 900) of claim 1, characterised in that : during the transition period (PT), a current flowing through the first transistor (T1) is substantially unstable; and during the steady period (PS), the current flowing through the first transistor (T1) is substantially stable.
  13. An operation method (1100) for an amplifier (100, 200, 500, 600, 800, 900), characterised in that : the amplifier (100, 200, 500, 600, 800, 900) comprises: a signal input terminal (NIN) configured to receive an input signal (SIN); a signal output terminal (NOUT) configured to output an amplified signal (SOUT); an amplification circuit (101, 201, 501, 601, 801, 901) coupled between the signal input terminal (NIN) and the signal output terminal (NOUT), the amplification circuit (101, 201, 501, 601, 801, 901) comprising a first transistor (T1), and the first transistor (T1) comprising a first terminal, a second terminal, a control terminal, and a body terminal, wherein the first terminal of the first transistor (T1) is coupled to a first node (N1), the second terminal of the first transistor (T1) is coupled to a second node (N2), the control terminal of the first transistor (T1) is coupled to the signal input terminal (NIN), and the body terminal of the first transistor (T1) is floating; and at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) coupled to the amplification circuit (101, 201, 501, 601, 801, 901); and the operation method (1100) comprises: during a transition period (PT), the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) providing a first voltage difference (VDS1) between the second terminal and the first terminal of the first transistor (T1) (Step 1110); and during a steady period (PS), the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) providing a second voltage difference (VDS2) between the second terminal and the first terminal of the first transistor (T1) (Step 1120); wherein the first voltage difference (VDS1) is greater than the second voltage difference (VDS2).
  14. The operation method (1100) of claim 13, characterised in that : the amplification circuit (201, 501, 601, 801, 901) further comprises: a second transistor (T2) comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor (T2) is coupled to the second node (N2), the second terminal of the second transistor (T2) is coupled to the signal output terminal (NOUT), and the control terminal of the second transistor (T2) is coupled to a third node (N3); and the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) comprises a first variable voltage generation circuit (210) coupled to the third node (N3) and a second variable voltage generation circuit (520, 620) coupled to the second node (N2); the method (1100) further comprises: the first variable voltage generation circuit (210) providing a first pulse voltage signal (VPS1) at the third node (N3); and the second variable voltage generation circuit (520, 620) providing a second pulse voltage signal (VPS2) at the second node (N2); wherein: during the transition period (PT), the first pulse voltage signal (VPS1) has a first voltage level (L1), the second pulse voltage signal (VPS2) has a third voltage level (L3); and during the steady period (PS), the first pulse voltage signal (VPS1) has a second voltage level (L2), the second pulse voltage signal (VPS2) has a fourth voltage level (L4).
  15. The operation method (1100) of claim 13, characterised in that : the at least one variable voltage generation circuit (110, 210, 520, 620, 830, 930) comprises a third variable voltage generation circuit (830, 930) coupled to the first node (N1); and the method (1100) further comprises: the third variable voltage generation circuit (830, 930) providing a third pulse voltage signal (VPS3) at the first node (N1); wherein: during the transition period (PT), the third pulse voltage signal (VPS3) has a fifth voltage level (L5); and during the steady period (PS), the third pulse voltage signal (VPS3) has a sixth voltage level (L6).

Description

Field of the Invention The disclosure relates to an amplifier and its operation method, and more particularly, to an amplifier that may quickly transition from a transient state to a steady state and its operation method. Background of the Invention Amplifiers are crucial components of radio-frequency (RF) transceiver circuits, used for amplifying RF signals. For example, amplifiers may include power amplifiers (PA) and low noise amplifiers (LNA). In a communication system, amplifiers may be disposed near an antenna and used to amplify a received signal. The performance of an amplifier may be evaluated by various parameters, such as gain, noise figure, linearity, power consumption, and stability. In amplifiers, to achieve a good noise figure, floating body transistors, where the body terminal is floating, may be used. In practical applications, amplifiers may be switched between various operating states. During these transitions, the threshold voltage of the floating body transistor may be less stable, causing the transistor's current (e.g., drain-source current) to stabilize slower, resulting in slower transition response of the amplifier. Observations indicate that increasing the voltage difference between the drain and source of the transistor may help the transistor stabilize quickly, thus stabilizing the drain-source current faster and improving the transition response of the amplifier. Therefore, there is a need for an amplifier that may be switched quickly between different operating modes while maintaining desirable performance parameters such as noise figure. Summary of the Invention The present invention is set out in the appended set of claims. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof: FIG.1 schematically shows an amplifier according to one embodiment of the disclosure;FIG.2 schematically shows an amplifier according to another embodiment of the disclosure;FIG.3 and FIG.4 schematically show waveform diagrams of voltage levels at some nodes of an amplifier according to an embodiment of the disclosure;FIG.5 schematically shows an amplifier according to another embodiment of the disclosure;FIG.6 schematically shows an amplifier according to another embodiment of the disclosure;FIG.7 schematically shows a waveform diagram of voltage levels at some nodes of an amplifier according to one embodiment of the disclosure;FIG.8 schematically shows an amplifier according to another embodiment of the disclosure;FIG.9 schematically shows an amplifier according to another embodiment of the disclosure;FIG.10 schematically shows a waveform diagram of voltage levels at some nodes of an amplifier according to an embodiment of the disclosure; andFIG.11 schematically shows a flowchart of an amplifier operation method according to an embodiment of the disclosure. Detailed Description Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and like reference numerals refer to like elements throughout. By referring to the following detailed description and in conjunction with the accompanying drawings, the invention may be understood. It should be noted that, for the ease of understanding by the readers and for the simplicity of the drawings, only part of the electronic device is illustrated in the drawings of this invention, and the specific elements in the drawings are not drawn to scale. Moreover, the quantity and size of the elements in the drawings are merely illustrative and are not intended to limit the scope of the invention. In the drawings, elements marked with the same reference symbol have the same or similar attributes or functions in the context. In the following specification and claims, terms such as "comprise," "include," and "have" are open terms, thus should be interpreted as "including but not limited to." Therefore, when the description of the present invention uses the terms "comprise," "include," and/or "have," they specify the presence of corresponding features, regions, steps, operations, and/or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations, and/or components. FIG.1 schematically shows an amplifier 100 according to an embodiment of the disclosure. As shown, the amplifier 100 includes a signal input terminal NIN, a signal output terminal NOUT, and an amplification circuit 101 coupled therebetween. For example, the signal input terminal NIN is coupled to a preceding circuit (e.g., an antenna) used to receive a signal SIN. The amplification circuit 101, for example, amplifies the signal SIN, and the signal output terminal