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EP-4742534-A2 - DIGITAL-TO-ANALOG CONVERTER

EP4742534A2EP 4742534 A2EP4742534 A2EP 4742534A2EP-4742534-A2

Abstract

A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.

Inventors

  • Tseng, Yi-Hung
  • NAGARAJAN, KARTHIK

Assignees

  • QUALCOMM Incorporated

Dates

Publication Date
20260513
Application Date
20200828

Claims (9)

  1. A phase locked loop (PLL) circuit, comprising: a phase detector configured to provide a control signal; a filter configured to receive the control signal and provide a frequency code word; a digitally controlled oscillator (DCO) configured to receive the frequency code word, the DCO having a digital-to-analog converter (DAC) circuit, and a ring oscillator, the DAC circuit comprising: a plurality of DAC transistor devices having an input side coupled to an output of the filter and an output side coupled to the ring oscillator; and a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances.
  2. The PLL circuit of claim 1, further comprising a control circuit configured to adjust a bias of the non-DAC transistor devices, wherein the control circuit comprises a resistance, a current source, and a reference non-DAC transistor device coupled to the non-DAC transistor devices, the reference non-DAC transistor device coupled to a bias operational amplifier (OpAmp) responsive to a reference voltage and a voltage at a drain of the reference non-DAC transistor device.
  3. The PLL circuit of claim 2, wherein the plurality of non-DAC transistor devices are biased in a triode region.
  4. The PLL circuit of claim 2, wherein the control circuit is configured to adjust a resistance of the plurality of non-DAC transistor devices.
  5. The PLL circuit of claim 2, further comprising an operating condition circuit coupled to the control circuit, the operating condition circuit having a current source that generates a sense current that is proportional to a current output (Idco) of the DAC, the sense current provided to the control circuit to allow the control circuit to adjust a resistance of at least one of the non-DAC transistor devices based on the current output (Idco) of the DAC.
  6. The PLL circuit of claim 5, wherein the current source comprises a plurality of transistor devices configured to generate a scaled current output (k*Idco) of the DAC.
  7. The PLL circuit of claim 2, further comprising an operating condition circuit coupled to the control circuit, the operating condition circuit having a current source that generates a sense current that is proportional to an input voltage level of the DAC, the sense current provided to the control circuit to allow the control circuit to adjust a resistance of at least one of the non-DAC transistor devices based on the input voltage level of the DAC.
  8. The PLL circuit of claim 7, wherein the current source comprises a plurality of transistor devices configured to generate a current related to the input voltage level of the DAC.
  9. The PLL circuit of claim 2, further comprising an operating condition circuit coupled to the control circuit, the operating condition circuit having a plurality of current sources that generate a sense current that is proportional to a current output (Idco) of the DAC and proportional to an input voltage level of the DAC, the sense current provided to the control circuit to allow the control circuit to adjust a resistance of at least one of the non-DAC transistor devices based on one or more of the current output (Idco) of the DAC and an input voltage level of the DAC.

Description

PRIORITY The present Application for patent claims priority to Non-provisional Application No. 16/577,074 entitled "DIGITAL-TO-ANALOG CONVERTER" filed September 20, 2019, assigned to the assignee hereof and hereby expressly incorporated by reference herein. FIELD The present disclosure relates generally to electronics, and more specifically to digital to analog converters. BACKGROUND Wireless communication devices and technologies are becoming ever more prevalent. Wireless communication devices generally transmit and receive communication signals. A communication signal is typically processed by a variety of different components and circuits. One of the circuits that process a communication signal is a phase locked loop (PLL). A PLL is a device that compares the phase and/or frequency of two different signals and generates an error signal that represents the phase and/or frequency difference between the two compared signals. When the two signals have different phase and/or frequencies, the phase and/or frequency difference between the two signals is constantly varying. The error signal is then used to control the phase and/or frequency of the loop, such that when the phase and/or frequency difference between the two signals is fixed, the two signals are at the same phase and/or frequency. A digital PLL (DPLL) typically includes a phase detector, and/or a frequency comparator or detector, a digitally controlled oscillator (DCO) that can adjust the frequency of the PLL based on a control voltage or current signal, a filter circuit, a feedback circuit, and may include other circuits, such as a buffer circuit, etc. The DCO may include a digital-to-analog converter (DAC) and an oscillator. The term "5G" refers to an evolving generation of wireless communication technology. One evolving technology is the ability to communicate over higher frequencies than LTE, such as at millimeter-wave (mmw) frequencies. For example, mmw signals are those that operate at extremely high frequencies, such as 20-30 Gigahertz (GHz) and beyond. A PLL designed to operate at mmw frequencies may be required to meet stringent design and/or performance specifications. A DCO included in the PLL similarly may have stringent design and/or performance specifications. It is desirable to provide a DAC with good performance. SUMMARY Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein. Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale. One aspect of the disclosure provides a digital to analog converter (DAC) including a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices. Another aspect of the disclosure provides a method for operating a digital-to-analog converter (DAC) including providing a variable resistance at an input side of a digital to analog converter (DAC), providing a signal indicative of a voltage headroom to a control circuit, and adjusting the variable resistance using the control circuit. Another aspect of the disclosure provides a device including means for providing a variable resistance at an input side of a digital to analog converter (DAC), means for providing a signal indicative of a voltage headroom, and means for adjusting the variable resistance based on the signal indicative of the voltage headroom. Another aspect of the disclosure provides a phase locked loop (PLL) circuit including a phase detector configured to provide a control signal, a filter configured to receive the control signal and provide a filtered voltage signal, and a digitally controlled oscillator (DCO) configured to receive the filtered voltage signal, the DCO having a digital-to-analog converter (DAC) circuit, and a ring oscillator. The DAC circuit includes a plurality of DAC transistor devices having an input side coupled to an output of the filter and an output side coupled to the ring oscillator, and a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances. BRIEF DESCRIPTION OF THE