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EP-4742541-A1 - A/D CONVERTER AND A/D CONVERSION METHOD

EP4742541A1EP 4742541 A1EP4742541 A1EP 4742541A1EP-4742541-A1

Abstract

An A/D converter performs an A/D conversion including a folding integral. The A/D converter includes a gain stage that generates a calculation value based on an input value, and an A/D conversion circuit that outputs a calculation value that can be used to generate a digital value by comparing the calculation value generated by the gain stage with a conversion reference voltage. The gain stage generates a calculation value V O (M-1) using an integral gain G(M-1) in the (M-1)_th integral operation among integral operations performed M times, and also generates a calculation value V O (M) using an integral gain G(M) in the M_th integral operation. The integral gain G(M-1) is greater than the integral gain G(M).

Inventors

  • KAWAHITO SHOJI

Assignees

  • NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY

Dates

Publication Date
20260513
Application Date
20240806

Claims (20)

  1. An A/D converter that performs an A/D conversion including a folding integral to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and an integral of a sampled value, comprising: a gain stage configured to output a calculation value based on the analog signal; and an A/D conversion circuit configured to output a result that is usable to generate the digital value by comparing the calculation value output by the gain stage with a conversion reference voltage, wherein the gain stage generates the calculation value based on the analog signal using a first integral gain in a k_th operation (k is an integer equal to or less than M-1) among the operations that are performed M times (M is an integer equal to or greater than 2), and generates the calculation value based on the analog signal using a second integral gain in a (k+1)_th operation, and the second integral gain is smaller than the first integral gain.
  2. The A/D converter according to claim 1, wherein the gain stage generates the calculation value based on the analog signal using a third integral gain in a first operation, and the third integral gain is greater than the first integral gain.
  3. The A/D converter according to claim 1, wherein the first integral gain is used in second to (M-1)_th operations, and the second integral gain is used in an M_th operation.
  4. The A/D converter according to claim 1, wherein the first integral gain is 1 or more and the second integral gain is 0 or more and less than 1.
  5. An A/D converter that performs an A/D conversion including a folding integral to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and an integral of a sampled value, comprising: a gain stage configured to output a calculation value based on the analog signal; and an A/D conversion circuit configured to output a result that is usable to generate the digital value by comparing the calculation value output by the gain stage with a conversion reference voltage, wherein the gain stage includes: a stage input configured to receive the analog signal; an operational amplifier circuit configured to generate the calculation value based on the analog signal; a stage output configured to output the calculation value to the A/D conversion circuit; a front stage capacitance part configured to be connectable to the stage input and an input of the operational amplifier circuit and including at least one front stage capacitor; and a feedback capacitance part configured to be connectable to the stage input and an output of the operational amplifier circuit and including one feedback capacitor, the gain stage selectively configures a first circuit and a second circuit different from the first circuit in the sampling of the input signal, the first circuit stores the analog signal in the at least one front stage capacitor by connecting the front stage capacitance part to the stage input, and stores the analog signal in the feedback capacitor by connecting the feedback capacitance part to the stage input, so that a ratio between a capacitance of the front stage capacitance part and a capacitance of the feedback capacitance part is set to a predetermined capacitance ratio, and the second circuit stores the analog signal in the at least one front stage capacitor by connecting the front stage capacitance part to the stage input, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitance part from the stage input, so that a ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is a capacitance ratio that is smaller than the capacitance ratio in the first circuit.
  6. The A/D converter according to claim 5, wherein the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part depends on a magnitude of the integral gain.
  7. The A/D converter according to claim 5, wherein the operations are performed M times (M is an integer equal to or greater than 2), and in the sampling of the input signal in a first operation, the first circuit is used so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to the predetermined capacitance ratio.
  8. The A/D converter according to claim 5, wherein the operations are performed M times (M is an integer equal to or greater than 2), and in the sampling of the input signal in second to (M-1)_th operations, the second circuit is used so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a capacitance ratio that is smaller than the predetermined capacitance ratio in the first circuit.
  9. The A/D converter according to claim 5, wherein the operations are performed M times (M is an integer equal to or greater than 2), and in the sampling of the input signal in second to (M-1)_th operations, the number of the front stage capacitors that store the analog signal in the second circuit is set to 2 or more, so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first circuit, and in the sampling of the input signal in an M_th operation, the number of the front stage capacitors that store the analog signal in the second circuit is set to 0 or 1, so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a second capacitance ratio that is smaller than the first capacitance ratio.
  10. The A/D converter according to claim 5, wherein a capacitance of the feedback capacitor is greater than a capacitance of the front stage capacitor.
  11. The A/D converter according to claim 5, wherein a capacitance of the feedback capacitor is greater than a capacitance of the first front stage capacitor, and the capacitance of the first front stage capacitor is different from the capacitance of a second front stage capacitor different from the first front stage capacitor.
  12. An A/D conversion method that performs an A/D conversion including a folding integral to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and an integral of a sampled value, the method comprising: generating a first calculation value based on the analog signal by performing the operations using a first integral gain; and generating a second calculation value based on the analog signal by performing the operations using a second integral gain after the generating of the first calculation value, wherein the second integral gain is smaller than the first integral gain.
  13. The A/D conversion method according to claim 12, further comprising generating a third calculation value based on the analog signal by performing the operations using a third integral gain before the generating of the first calculation value, wherein the third integral gain is greater than the first integral gain.
  14. The A/D conversion method according to claim 12, wherein the operations are performed M times (M is an integer equal to or greater than 2), in second to (M-1)_th operations, the generating of the first calculation value is performed, and in an M_th operation, the generating of the second calculation value is performed.
  15. The A/D conversion method according to claim 12, wherein the first integral gain is 1 or more and the second integral gain is 0 or more and less than 1.
  16. An A/D conversion method that performs an A/D conversion including a folding integral to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and an integral of a sampled value, the method comprising: a sampling step of the input signal for storing the analog signal at least in a front stage capacitance part that is connectable to a stage input of a gain stage that outputs a calculation value based on the analog signal among the front stage capacitance part including at least one front stage capacitor and a feedback capacitance part including one feedback capacitor; and an integral step of a sampled value for generating the calculation value at an output of the operational amplifier circuit by connecting at least the front stage capacitance part to an input of the operational amplifier circuit included in the gain stage, wherein in the sampling step of the input signal, either a first storage or a second storage different from the first storage is performed, the first storage stores the analog signal in the at least one front stage capacitor by connecting the front stage capacitance part to the stage input and stores the analog signal in the feedback capacitor by connecting the feedback capacitance part to the stage input, so that a ratio between a capacitance of the front stage capacitance part and a capacitance of the feedback capacitance part is set to a predetermined capacitance ratio, and the second storage stores the analog signal in the at least one front stage capacitor by connecting the front stage capacitance part to the stage input and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitance part from the stage input, so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage.
  17. The A/D conversion method according to claim 16, wherein the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part depends on a magnitude of the integral gain.
  18. The A/D conversion method according to claim 16, wherein the operations are performed M times (M is an integer equal to or greater than 2), and in the sampling step of the input signal in a first operation, the first storage is performed so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to the predetermined capacitance ratio.
  19. The A/D conversion method according to claim 16, wherein the operations are performed M times (M is an integer equal to or greater than 2), and in the sampling step of the input signal in second to (M-1)_th operations, the second storage is performed so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage.
  20. The A/D conversion method according to claim 16, wherein the operations are performed M times (M is an integer equal to or greater than 2), in the sampling of the input signal in second to (M-1)_th operations, the number of the front stage capacitors that store the analog signal in the second storage is set to 2 or more, so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage, and in the sampling of the input signal in an M_th operation, the number of the front stage capacitors that store the analog signal in the second storage is set to 0 or 1, so that the ratio between the capacitance of the front stage capacitance part and the capacitance of the feedback capacitance part is set to a second capacitance ratio that is smaller than the first capacitance ratio.

Description

Technical Field The present disclosure relates to an A/D converter and an A/D conversion method. Background Art Patent Literature 1 to 6 disclose A/D converters that generate digital values from analog signals. For example, the A/D converters disclosed in Patent Literature 1 to 4 perform a folding integral type A/D conversion operation and a cyclic type A/D conversion operation by switching a switch. Specifically, the A/D converters first perform the folding integral type A/D conversion operation. Next, the A/D converters perform the cyclic type A/D conversion operation on an analog signal that is a calculation result of the folding integral type A/D conversion. Citation List Patent Literature [Patent Literature 1] PCT International Publication No. WO2018-088476[Patent Literature 2] Japanese Unexamined Patent Application No. 2017-201751[Patent Literature 3] Japanese Unexamined Patent Application No. 2017-139583[Patent Literature 4] PCT International Publication No. WO2012-111821[Patent Literature 5] Japanese Unexamined Patent Application No. 2017-55174[Patent Literature 6] Japanese Unexamined Patent Publication No. 2007-49637 Summary of Invention Technical Problem As in the A/D converters disclosed in Patent Literature 1 to 4, when the switching between the folding integral type and the cyclic type is performed by switching a switch, the calculation result (the analog signal) of the folding integral type which is an operation in a previous stage is kept within a range acceptable in the cyclic type which is an operation in a subsequent stage. Therefore, in the folding integral type operation, an integral gain is employed such that the calculation result of the integral operation is kept within a desired range. The integral gain affects the effectiveness of noise reduction in the integral operation. As the integral gain increases, the effectiveness of noise reduction becomes higher. However, as the integral gain decreases, the effectiveness of noise reduction becomes lower. In other words, when it is necessary to keep the calculation result of the integral operation within the desired range, it becomes necessary to reduce the integral gain. As a result, the effectiveness of noise reduction is reduced. The present disclosure describes an A/D converter and an A/D conversion method that can obtain a good effectiveness of noise reduction while the calculation result of integral operation is kept within a desired range. Solution to Problem One aspect of the present disclosure is an A/D converter that performs an A/D conversion including a folding integral to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and an integral of a sampled value. The A/D converter includes a gain stage configured to output a calculation value based on the analog signal, and an A/D conversion circuit configured to output a result that is usable to generate the digital value by comparing the calculation value output by the gain stage with a conversion reference voltage. The gain stage generates the calculation value based on the analog signal using a first integral gain in a k_th operation (k is an integer equal to or less than M-1) among the operations that are performed M times (M is an integer equal to or greater than 2). The gain stage generates the calculation value based on the analog signal using a second integral gain in a (k+1)_th operation. The second integral gain is smaller than the first integral gain. The A/D converter makes the integral gain of the k_th integral operation, which corresponds to the next integral operation, smaller than the integral gain of the (k-1)_th integral operation among the plurality of integral operations. In other words, in order to keep the calculation value obtained by the M integral operations within the predetermined value, the A/D converter does not suppress the integral gain in all of the M integral operations, but suppresses the integral gain in the subsequent integral operations in which the calculation value becomes larger. As a result, a sufficient integral gain is obtained in the (k-1) _th integral operation or the like in which the integral gain is not suppressed. As a result, the effectiveness of noise reduction can be sufficiently ensured. The integral gain of the subsequent integral operation is suppressed. As a result, it is possible to prevent the calculation value obtained as a result of the M integral operations from being larger than a predetermined value. In other words, the A/D converter can obtain a good effectiveness of noise reduction while keeping the calculation result of the integral operation within a desired range. In one aspect, the gain stage may generate the calculation value based on the analog signal using a third integral gain in a first operation. The third integral gain may be greater than the first integral gain. With such a configuration, it is possible to obtain an even better effectivenes