EP-4742542-A1 - DELTA-SIGMA MODULATORS WITH DOWNSAMPLED DIGITAL INTEGRATORS

EP4742542A1EP 4742542 A1EP4742542 A1EP 4742542A1EP-4742542-A1

Abstract

Systems and methods for delta-sigma modulators with downsampled digital integrators. In various embodiments, a delta-sigma modulator may include: a comparator configured to receive an analog input and to provide a digital output at a sampling frequency, where the digital output is applied to an integrator path and to a feed-forward path; a digital integrator in the integrator path, where the digital integrator is configured to operate with a clock frequency that is less the sampling frequency; and a summer configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.

Inventors

van der KLOOSTER, Jan Daniël

Assignees

NXP B.V.

Dates

Publication Date: 20260513
Application Date: 20251111

Claims (15)

A delta-sigma modulator, comprising: a comparator configured to receive an analog input and to provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and to a feed-forward path; a digital integrator in the integrator path, wherein the digital integrator is configured to operate with a clock frequency that is less the sampling frequency; and a summer configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.
The delta-sigma modulator of claim 1, further comprising a downsampler in the integrator path, wherein the downsampler is configured to provide a downsampled digital signal at the clock frequency to the digital integrator.
The delta-sigma modulator of claim 1 or 2, further comprising an accumulator in the integrator path, wherein the accumulator is configured to receive the digital output and to provide a running sum of the digital output.
The delta-sigma modulator of claim 3, wherein the accumulator comprises a Finite Impulse Response, FIR, filter.
The delta-sigma modulator of claim 3 or 4, wherein the accumulator outputs an average of n values upon receipt of the nth value, and wherein the digital amplifier is configured to divide the output by n.
The delta-sigma modulator of any of claims 3 to 5, further comprising a digital amplifier coupled to the accumulator in the integrator path, wherein the digital amplifier is configured to normalize the running sum of the digital output and to provide a running average of the digital output.
The delta-sigma modulator of claim 6, further comprising a truncator coupled between the accumulator and the digital integrator, wherein the truncator is configured to reduce a bit width of an output of the accumulator.
The delta-sigma modulator of any preceding claim, further comprising a truncator coupled between the digital integrator and the summer, wherein the truncator is configured to reduce a bit width of an output of the digital integrator.
The delta-sigma modulator of any preceding claim, further comprising a digital amplifier in the feed-forward path.
The delta-sigma modulator of any preceding claim, wherein the integrator path adds a pole to a transfer function of the delta-sigma modulator, and wherein the feed-forward path adds a zero configured to compensate for the pole.
The delta-sigma modulator of any preceding claim, wherein the comparator is configured to receive the analog input through a loop filter.
In an Analog-to-Digital Converter, ADC, a method comprising: producing a digital output using a comparator operating at a sampling frequency; providing the digital output to an integration path and to a feed-forward path; downsampling the data of the integration path to a lower frequency than the sampling frequency; integrating the data of the integration path with a digital integrator after the downsampling; and combining the integrated downsampled data of the integration path with the digital output to produce a bitstream.
The method of claim 12, further comprising the comparator receiving an analog input through a loop filter and producing the digital output based on the analog input at the sampling frequency.
The method of claim 12 or 13, wherein downsampling the digital output comprises downsampling a running average of the digital output.
The method of claim 14, wherein downsampling the running average of the digital output further comprises: truncating the running average of the digital output; and downsampling the truncated, running average of the digital output.

Description

Field This disclosure relates generally to electronic circuits, and more specifically, to delta-sigma modulators with downsampled digital integrators. Background Within the class of analog-to-digital converters (ADC), a category exists which employs oversampling techniques to achieve high-resolution digital outputs. Traditionally, in such ADCs, the analog-to-digital domain (e.g., quantizer(s)) crossing and the digital-to-analog domain (e.g., feedback circuit(s)) employ the same number of levels or bits, where a multi-level approach increases complexity. Alternatively, an approach exists where the number of quantizer levels is less than the feedback levels, however, this has proven difficult to realize due to stability issues. As the inventor hereof has recognized, ADCs with more feedback levels than quantization levels encounter challenges in maintaining stability, particularly when its digital components operate at the same clock frequency. Conventional solutions, such as analog compensation or digital feed-forward, require significant hardware resources and result in increased noise. Brief Description of the Drawings The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 is a high-level block diagram of an example of a delta-sigma modulator according to some embodiments.FIG. 2 is a detailed block diagram of an example of a delta-sigma modulator according to some embodiments.FIG. 3 is a flowchart of an example of a method for operating a delta-sigma modulator according to some embodiments.FIG. 4 is a circuit diagram of an example implementation of a delta-sigma modulator according to some embodiments.FIG. 5 is a circuit diagram of another example implementation of a delta-sigma modulator according to some embodiments. Detailed Description Analog-to-digital converters (ADCs) are essential components in modern electronics, enabling the conversion of analog signals into digital data for processing and analysis. Among the various types of ADCs, delta-sigma modulators are often favored for their ability to achieve high resolution and accuracy through oversampling and noise shaping. These modulators are widely used in applications such as audio processing, telecommunications, and instrumentation, where precision and dynamic range are important, and data rates are typically low. Conventional delta-sigma modulators utilize a single-bit comparator or quantizer and feedback digital-to-analog converter (DAC) to digitize analog signals through oversampling. While multi-bit comparators can sometimes achieve the same quantization precision with a lower oversampling ratio, they also introduce non-linearity due to mismatches between levels within the comparator and mismatches between levels within the feedback DAC. A digital integrator allows the use of a single-bit comparator, which is inherently linear, but still requires a potentially non-linear multi-bit feedback DAC. In order to linearize domain crossings (analog-to-digital or digital-to-analog) mismatch shaping techniques may be employed for this purpose, such as Dynamic Element Matching (DEM) algorithms. In many cases linearizing the digital-to-analog crossing in the form of a feedback DAC is simpler than linearizing the analog-to-digital crossing in the form of a comparator. DEM techniques may improve the linearity of a DAC, reducing or minimizing the effects of component mismatches by dynamically selecting and averaging the use of DAC elements over time, thereby effectively spreading mismatch errors across the Nyquist bandwidth. An advantage of a multi-bit feedback DAC in delta-sigma modulators is its ability to coarsely track the analog input, allowing oversampling without covering the full input range. In current systems, however, multi-bit comparators increase the design complexity of the delta-sigma modulator significantly. Alternatively, in current systems, a digital integrator is used and operated at the same frequency as the comparator, which makes the whole sigma delta loop difficult to stabilize as the integrator introduces a pole in the feedback loop. The transfer function of a delta-sigma modulator, represented in the discrete and continuous time domains (for z and s, respectively) characterizes how input signals and quantization noise propagate through the system, and it is shaped by strategically placing poles and zeros within the transfer function. Poles (locations in the z or s-domains where the transfer function goes to infinity) are often placed to enhance shape the quantization noise. Zeros (locations in the z or s-domains where the transfer function goes to zero), on the other hand, are selected to control the stability and impulse response of the system. In the case of a delta-sigma modulator's digital integrator introducing a