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EP-4742694-A1 - IMAGE SENSOR AND OPERATION METHOD THEREOF

EP4742694A1EP 4742694 A1EP4742694 A1EP 4742694A1EP-4742694-A1

Abstract

An image sensor includes first and second pixels. The first pixel includes a first photodiode, a first transfer gate connected between the first photodiode and a first floating diffusion (FD) node, a first FD selection gate connected between a first node and the first FD node, a first lateral overflow integration capacitor (LOFIC) selection gate connected between the first FD node and a first LOFIC node, and a first capacitor connected between the first LOFIC node and a first reset voltage. The second pixel includes a second photodiode, a second transfer gate connected between the second photodiode and a second FD node, and a second FD selection gate connected between a second node electrically connected to the first node and the second FD node.

Inventors

  • HUH, JINSUK
  • JANG, DONGYOUNG

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260513
Application Date
20251030

Claims (15)

  1. An image sensor (100) comprising: a first pixel (PIX1) including a first photodiode (PD1), the first pixel (PIX1) configured to output a first output voltage corresponding to light incident onto the first photodiode (PD1); and a second pixel (PIX2) including a second photodiode (PD2), the second pixel (PIX2) configured to output a second output voltage corresponding to light incident onto the second photodiode (PD2), wherein the first pixel (PIX1) further includes, a first transfer gate (TG1) connected between the first photodiode (PD1) and a first floating diffusion (FD) node (n_FD1), a first FD selection gate (FDSG1) connected between a first node (n1) and the first FD node (n_FD1), a first lateral overflow integration capacitor (LOFIC) selection gate (LoSG1) connected between the first FD node (n_FD1) and a first LOFIC node (n_Lo1), and a first capacitor (CAP1) connected between the first LOFIC node (n_Lo1) and a first reset voltage (VRST1), and wherein the second pixel (PIX2) further includes, a second transfer gate (TG2) connected between the second photodiode (PD2) and a second FD node (n_FD2), a second FD selection gate (FDSG2) connected between a second node (n2) electrically connected to the first node (n1) and the second FD node (n_FD2), a second LOFIC selection gate (LoSG2) connected between the second FD node (n_FD2) and a second LOFIC node (n_Lo2), and a second capacitor (CAP2) connected between the second LOFIC node (n_Lo2) and the first reset voltage (VRST1).
  2. The image sensor (100) of claim 1, wherein the first capacitor (CAP1) includes at least one of a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, a metal-oxide-semiconductor capacitor (MOSCAP), a polysilicon capacitor, and a DRAM capacitor, and the second capacitor includes at least one of a MIM capacitor, a MOM capacitor, a MOSCAP, a polysilicon capacitor, and a DRAM capacitor.
  3. The image sensor (100) of claim 1 or claim 2, wherein, in response to the image sensor operating in an LOFIC mode in which the first and second FD selection gates (FDSG1, FDSG2) are configured to be turned off, the first and second LOFIC selection gates (LoSG1, LoSG2) are configured to be turned on, the first FD node (n_FD1) and the first capacitor (CAP1) are configured to be electrically connected, and the second FD node (n_FD2) and the second capacitor (CAP2) are configured to be electrically connected.
  4. The image sensor (100) of claim 3, wherein the first pixel (PIX1) further includes, a first LOFIC reset gate (LoRG1) connected between the first LOFIC node (n_Lo1) and a second reset voltage (VRST2), and a first discharge switch (DSW1) connected between the first reset voltage (VRST1) and the second reset voltage (VRST2), and wherein the second pixel (PIX2) further includes, a second LOFIC reset gate (LoRG2) connected between the second LOFIC node (n_FD2) and the second reset voltage (VRST2), and a second discharge switch (DSW2) connected between the first reset voltage (VRST1) and the second reset voltage (VRST2).
  5. The image sensor (100) of claim 4, wherein, in response to the image sensor (100) operating in the LOFIC mode, the first FD node (n_FD1) and the first capacitor (CAP1) are configured to be reset through the first LOFIC reset gate (LoRG1) and the first discharge switch (DSW1), and the second FD node (n_FD2) and the second capacitor (CAP2) are configured to be reset through the second LOFIC reset gate (LoRG2) and the second discharge switch (DSW2).
  6. The image sensor (100) of claim 1 or claim 2, wherein the first pixel (PIX1) further includes, a first LOFIC reset gate (LoRG1a) connected between the first LOFIC node (n_Lo1a) and a third LOFIC node (n_Lolb), a third LOFIC reset gate (LoRG1b) connected between the third LOFIC node (n_Lolb) and a second reset voltage (VRST2), a first discharge switch (DWS1) connected between the first reset voltage (VRST1) and the second reset voltage (VRST2), and a third capacitor (CAP1b) connected between the third LOFIC node (n_Lolb) and the first reset voltage (VRST1), and wherein the second pixel (PIX2) further includes: a second LOFIC reset gate (LoRG2a) connected between the second LOFIC node (n_Lo2a) and a fourth LOFIC node (n_Lo2b), a fourth LOFIC reset gate (LoRG2b) connected between the fourth LOFIC node (n_LoRG2b) and the second reset voltage (VRST2), a second discharge switch (DSW2) connected between the first reset voltage (VRST1) and the second reset voltage (VRST2), and a fourth capacitor (CAP2b) connected between the fourth LOFIC node (n_Lo2b) and the first reset voltage (VRST1).
  7. The image sensor (100) of any preceding claim, wherein, in response to the image sensor (100) operating in a shared mode in which the first and second LOFIC selection gates (LoSG1, LoSG2) are configured to be turned off and the first and second FD selection gates (FDSG1, FDSG2) are configured to be turned on, the first and second FD nodes (n_FD1, n_FD2) are configured to be electrically connected.
  8. The image sensor (100) of claim 7, wherein the first pixel (PIX1) further includes a first reset gate (RG1) connected between the first node (n1) and a pixel voltage (VPIX), and the second pixel (PIX2) further includes a second reset gate (RG2) connected between the second node (n2) and the pixel voltage (VPIX).
  9. The image sensor (100) of claim 8, wherein, in response to the image sensor (100) operating in the shared mode, the first and second FD nodes (n_FD1, n_FD2) are configured to be reset through the first reset gate (RG1) and the second reset gate (RG2).
  10. The image sensor (100) of any of claims 1-7, wherein the first pixel (PIX1) further includes, a first reset gate (RG1) connected between the first node (n1) and a third FD node (n_FDa), and a third reset gate (LRG1) connected between the third FD node (n_FDa) and a pixel voltage (VPIX), and the second pixel (PIX2) further includes, a second reset gate (MRG2) connected between the second node (n2) and a fourth FD node (n_FDb), and a fourth reset gate (LRG2) connected between the fourth FD node (n_FDb) and the pixel voltage (VPIX).
  11. The image sensor of any preceding claim, wherein the first pixel (PIX1) further includes, a third photodiode (LPD1), and a third transfer gate (LTG1) connected between the third photodiode (LPD1) and the first FD node (n_FD1), and the second pixel (PIX2) further includes. a fourth photodiode (LPD2); and a fourth transfer gate (LTG2) connected between the fourth photodiode (LPD2) and the second FD node (n_FD2).
  12. The image sensor (100) of any preceding claim, further comprising: a third pixel including a third photodiode, the third pixel configured to output a third output voltage corresponding to the light incident onto the third photodiode, wherein the third pixel further includes, a third transfer gate connected between the third photodiode and a third FD node; a third FD selection gate connected between a third node electrically connected to the first and second nodes (n1, n2) and the third FD node, a third LOFIC selection gate connected between the third FD node and a third LOFIC node, and a third capacitor connected between the third LOFIC node and a third reset voltage.
  13. The image sensor (100) of any preceding claim, wherein the first pixel (PIX1) further includes a first source follower (SF1) and a first selection gate (SG1) connected in series between a pixel voltage (VPIX) and a first column line (CL1), a gate terminal of the first source follower (SF1) is connected to the first FD node (n_FD1), the second pixel (PIX2) further includes a second source follower (SF2) and a second selection gate (SG2) connected in series between the pixel voltage (VPIX) and the first column line (CL1), a gate terminal of the second source follower (SF2) is connected to the second FD node (n_FD2), and the first column line (CL1) is configured to output each of the first and second output voltages.
  14. The image sensor (100) of any of claims 1-12, wherein the first pixel (PIX1) further includes a first source follower (SF1) and a first selection gate (SG1) connected in series between a pixel voltage (VPIX) and a first column line (CL1), a gate terminal of the first source follower (SF1) is connected to the first FD node (n_FD1), the second pixel (PIX2) further includes a second source follower (SF2) and a second selection gate (SG2) connected in series between the pixel voltage (VPIX) and a second column line, a gate terminal of the second source follower (SF2) is connected to the second FD node (n_FD2), the first column line (CL1) is configured to output the first output voltage, and the second column line is configured to output the second output voltage.
  15. The image sensor (100) of any preceding claim, further comprising: a first semiconductor die (DIE_T); and a second semiconductor die (DIE_M) stacked on the first semiconductor die (DIE_T), and configured to be electrically connected to the first semiconductor die (DIE_T) through a connection structure, wherein the first photodiode (PD1) and the second photodiode (PD2) are in the first semiconductor die (DIE_T), and wherein the first capacitor (CAP1) and the second capacitor (CAP2) are in the second semiconductor die (DIE_M).

Description

TECHNICAL FIELD Some example embodiments described herein relate to an image sensor, and more particularly, relate to an image sensor and/or an operation method thereof. BACKGROUND An image sensor obtains image information about an external object by converting a light reflected from the external object into an electrical signal. An electronic device which includes the image sensor may display an image in a display panel by using the obtained image information. The image sensor may be mounted in various types of electronic devices. For example, the electronic device which includes the image sensor may be included as a component of various types of electronic devices such as a smartphone, a tablet personal computer (PC), a laptop PC, and/or a wearable device. SUMMARY Some example embodiments provide an image sensor with improved performance and improved reliability and/or an operation method thereof. According to some example embodiments, an image sensor includes a first pixel including a first photodiode, the first pixel configured to output a first output voltage corresponding to a light incident onto the first photodiode, and a second pixel including a second photodiode, the second pixel configured to output a second output voltage corresponding to the light incident onto the second photodiode. The first pixel further includes a first transfer gate connected between the first photodiode and a first floating diffusion (FD) node, a first FD selection gate connected between a first node and the first FD node, a first lateral overflow integration capacitor (LOFIC) selection gate connected between the first FD node and a first LOFIC node, and a first capacitor connected between the first LOFIC node and a first reset voltage. The second pixel further includes a second transfer gate connected between the second photodiode and a second FD node, a second FD selection gate connected between a second node electrically connected to the first node and the second FD node, a second LOFIC selection gate connected between the second FD node and a second LOFIC node, and a second capacitor connected between the second LOFIC node and the first reset voltage. According to some example embodiments, an operation method of an image sensor is provided, the image sensor including a first pixel and a second pixel, the first pixel including a first photodiode, a first floating diffusion (FD) node, a first shared floating diffusion (SFD) circuit connected to the first FD node, and a first lateral overflow integration capacitor (LOFIC) circuit connected to the first FD node, and the second pixel including a second photodiode, a second FD node, a second SFD circuit connected to the second FD node, and a second LOFIC circuit connected to the second FD node. The operation method includes electrically connecting the first FD node and the second FD node by disabling the first LOFIC circuit and enabling the first SFD circuit and performing a sensing operation on the first pixel based on the first and second FD nodes, in a shared mode, and electrically connecting the first FD node and a first capacitor included in the first LOFIC circuit by disabling the first SFD circuit and enabling the first LOFIC circuit and performing a sensing operation on the first pixel based on the first FD node and the first capacitor, in an LOFIC mode. During the sensing operation on the first pixel in the shared mode, the first capacitor is electrically separated from the first FD node. During the sensing operation on the first pixel in the LOFIC mode, the second FD node is electrically separated from the first FD node. According to some example embodiments, an image sensor includes a first photodiode, a first transfer gate connected between the first photodiode and a first floating diffusion (FD) node, a first shared floating diffusion (SFD) circuit connected to the first FD node, a first lateral overflow integration capacitor (LOFIC) circuit connected to the first FD node and including a first capacitor, a first source follower including a first gate terminal connected to the first FD node, and a first selection gate connected between the first source follower and a first column line. The image sensor is configured to operate in a shared mode and in a LOFIC mode, such that, in the shared mode, the first SFD circuit is configured to electrically connect the first FD node to a second FD node different from the first FD node, and in the LOFIC mode of the image sensor, the first LOFIC circuit is configured to electrically connect the first FD node to the first capacitor. According to some example embodiments, an image sensor includes a first pixel including a first photodiode, a first floating diffusion (FD) node, and a first capacitor, and a second pixel including a second photodiode, a second FD node, and a second capacitor. The image sensor is configured to operate in a shared mode and in a lateral integration overflow capacitor (LOFIC) mode such that, in the sh