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EP-4742849-A1 - SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME

EP4742849A1EP 4742849 A1EP4742849 A1EP 4742849A1EP-4742849-A1

Abstract

A semiconductor device includes a first semiconductor structure (S1) and a second semiconductor structure (S2). The first semiconductor structure (S1) includes circuit elements (120) on a first substrate (101), a lower interconnection structure (130) coupled with the circuit elements (120), and a lower bonding structure (180) coupled with the lower interconnection structure (130). The second semiconductor structure (S2) includes an upper bonding structure (280) bonded to the lower bonding structure (180), a conductive layer (201), a stack structure (GS1, GS2) including interlayer insulating layers (220) and gate electrodes (230), a plurality of separation regions (MS) at least partially penetrating through the stack structure (GS1, GS2), channel structures (CH) including a channel layer and at least partially penetrating through the stack structure (GS1, GS2), a plurality of address studs (275) spaced apart from each other by a first separation distance, a plurality of channel studs (272) below the channel structures (CH), and an upper interconnection structure (271, 273, 274) below the stack structure (GS1, GS2), coupled with the plurality of channel studs (272), and spaced apart from the plurality of address studs (275).

Inventors

  • PARK, BYUNGGON
  • OH, Hyunsyek
  • PARK, Junbeom
  • Shin, Yongjoon
  • OH, Soosik
  • KIM, Moongeun

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260513
Application Date
20250825

Claims (15)

  1. A semiconductor device, comprising: a first semiconductor structure (S1) comprising: a first substrate (101); circuit elements (120) on the first substrate (101); a lower interconnection structure (130) coupled with the circuit elements (120); and a lower bonding structure (180) coupled with the lower interconnection structure (130); and a second semiconductor structure (S2) comprising: an upper bonding structure (280) bonded to the lower bonding structure (180); a conductive layer (201); a stack structure (GS1, GS2) comprising interlayer insulating layers (220) and gate electrodes (230) laminated in a first direction (Z) below the conductive layer (201), the first direction (Z) being perpendicular to an upper surface of the conductive layer (201); a plurality of separation regions (MS) at least partially penetrating through the stack structure (GS1, GS2), extending in a second direction (X), and spaced apart from each other in a third direction (Y), the second direction (X) being perpendicular to the first direction (Z), the third direction (Y) being perpendicular to the first direction (Z) and the second direction (X); channel structures (CH) comprising a channel layer (240) and at least partially penetrating through the stack structure (GS1, GS2) in the first direction (Z); a plurality of address studs (275) spaced apart from each other by a first separation distance (I1) in the second direction (X) below at least one separation region (MS) of the plurality of separation regions (MS); a plurality of channel studs (272) below the channel structures (CH); and an upper interconnection structure (271, 273, 274) below the stack structure (GS1, GS2), coupled with the plurality of channel studs (272), and spaced apart from the plurality of address studs (275).
  2. The semiconductor device of claim 1, wherein each address stud (275) of the plurality of address studs (275) comprises a first upper surface (Sb), a first lower surface, and a first side surface between the first upper surface (Sb) and the first lower surface, wherein each channel stud (272) of the plurality of channel studs (272) comprises a second upper surface, a second lower surface, and a second side surface between the second upper surface and the second lower surface, and wherein the first lower surfaces of the plurality of address studs (275) are disposed on a same level as the second lower surfaces of the plurality of channel studs (272).
  3. The semiconductor device of claim 2, wherein the first upper surfaces (Sb) of the plurality of address studs (275) are disposed below third lower surfaces (Sa) of the at least one separation region (MS), wherein, for each address stud (275) of the plurality of address studs (275), a width of the first upper surface (Sb) is less than a width (W2) of the first lower surface, and wherein widths (W1) of the third lower surfaces (Sa) of the at least one separation region (MS) are greater than the width (W2) of the first lower surface of each address stud of the plurality of address studs (275).
  4. The semiconductor device of claim 3, wherein the third lower surfaces (Sa) of the at least one separation region (MS) are spaced apart from the first upper surface (Sb) of each address stud (275) of the plurality of address studs (275) in the first direction (Z).
  5. The semiconductor device of claim 3 or 4, further comprising: a base layer (298) between the third lower surfaces (Sa) of the at least one separation region (MS) and the first upper surface (Sb) of each address stud (275) of the plurality of address studs (275).
  6. The semiconductor device of any one of claims 2 to 5, wherein, for each address stud (275) of the plurality of address studs (275), a first reference line (ℓ 1 ) passing through a center of the upper surface in the first direction (Z) is offset with respect to a second reference line (ℓ 0 ) passing through a center of a width of the at least one separation region (MS) in the third direction (Y).
  7. The semiconductor device of any one of claims 2 to 6, further comprising: an upper insulating layer (295) between the first lower surface of each address stud (275) of the plurality of address studs (275) and the upper interconnection structure (271, 273, 274), wherein the plurality of address studs (275) are isolated from the upper interconnection structure (271, 273, 274) by the upper insulating layer (295).
  8. The semiconductor device of any one of claims 1 to 7, wherein a first length (h1) of each address stud (275) of the plurality of address studs (275) in the first direction (Z) is equal to a second length (h1) of each channel stud (272) of the plurality of channel studs (272) in the first direction (Z).
  9. The semiconductor device of any one of claims 1 to 7, wherein a first length (h2) of each address stud (275) of the plurality of address studs (275) in the first direction (Z) is less than a second length (h1) of each channel stud (272) of the plurality of channel studs (272) in the first direction (Z).
  10. The semiconductor device of any one of claims 1 to 9, wherein the upper interconnection structure (271, 273, 274) comprises bit lines (BL) coupled with the plurality of channel studs (272), extending in the third direction (Y) and spaced apart from each other in the second direction (X), and wherein the first separation distance (I1) is a multiple of a pitch of the bit lines (BL).
  11. The semiconductor device of claim 1, further comprising: an upper gate electrode (293) between the channel structures (CH) and the plurality of channel studs (272); upper channel structures (CH3) at least partially penetrating through the upper gate electrode (293) and coupled with each of the channel structures (CH); and insulating regions (SS) at least partially penetrating through the upper gate electrode (293) and disposed below the plurality of separation regions (MS), wherein the plurality of address studs (275) are disposed below the insulating regions (SS).
  12. The semiconductor device of claim 11, wherein a first reference line (ℓ 1 ) passing through a center of an upper surface of an address stud (275) of the plurality of address studs (275) in the first direction (Z) is coaxial with a second reference line (ℓ 0 ) passing through a center of a width of a separation region (MS) of the at least one separation region (MS) in the third direction (Y) and is offset in the third direction (Y) from a third reference line (ℓ 2 ) passing through a center of a width of an insulating region (SS) of the insulating regions (SS) which is closest to the address stud (275) in the third direction (Y).
  13. The semiconductor device of claim 11 or 12, wherein a width of the upper surface (Sb) of each address stud (275) of the plurality of address studs (275) is less than a width of a lower surface of each separation region (SS) of the plurality of separation regions (MS).
  14. The semiconductor device of any one of claims 1 to 13, wherein the plurality of separation regions (MS) comprise address separation groups comprising first address separation regions (MSc) and second address separation regions (MSc) adjacent to the first address separation regions in the third direction (Y); the plurality of address studs (275) spaced apart from each other by multiples (r) of a unit separation distance (I1) in the second direction (X), and disposed below the first address separation regions (MSc) and the second address separation regions (MSc).
  15. A data storage system, comprising: a semiconductor storage device (1110) according to any one of the preceding claims; and a controller (1200), wherein the semiconductor storage device (1110) further comprises an input/output pad (1101) coupled with the circuit elements (120), and wherein the controller (1200) is coupled with the semiconductor storage device (1100) via the input/output pad (1101) and configured to control the semiconductor storage device (1200).

Description

BACKGROUND 1. Field The present disclosure relates generally to semiconductor devices, and more particularly, to a semiconductor device and data storage systems including the same. 2. Description of Related Art Data storage systems, which may need data storage, may use a semiconductor device that may be capable of storing a relatively large amount of data. Accordingly, approaches for potentially increasing the data storage capacity of a semiconductor device may have been researched. For example, a possible approach for potentially increasing the data storage capacity of a semiconductor device may include three-dimensionally arranging memory cells of a semiconductor device, rather than arranging the memory cells two-dimensionally. SUMMARY One or more example embodiments of the present disclosure may provide a semiconductor device having a relatively high reliability compared to a related semiconductor device and a data storage system including such a semiconductor device. One or more example embodiments of the present disclosure may provide a semiconductor device that has structural features that can be used for improving error inspection and consequently for improving the reliability of the device, and a data storage system including such a semiconductor device. According to an aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes laminated in a first direction below the conductive layer, a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, channel structures including a channel layer and at least partially penetrating through the stack structure in the first direction, a plurality of address studs spaced apart from each other by a first separation distance in the second direction below at least one separation region of the plurality of separation regions, a plurality of channel studs below the channel structures, and an upper interconnection structure below the stack structure, coupled with the plurality of channel studs, and spaced apart from the plurality of address studs. The first direction is perpendicular to an upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. According to an aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes stacked in a first direction below the conductive layer, channel structures including a channel layer and at least partially penetrating through the stack structure in the first direction, a plurality of separation regions at least partially penetrating through the stack structure, extending in a second direction, and spaced apart from each other in a third direction, a plurality of address studs spaced apart from each other by multiples of a unit separation distance in the second direction, and disposed below the first address separation regions and the second address separation regions, and a plurality of channel studs disposed below the channel structures. The first direction is perpendicular to an upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. The plurality of separation regions include address separation groups including first address separation regions and second address separation regions adjacent to the first address separation regions in the third direction. According to an aspect of the present disclosure, a data storage system includes a semiconductor storage device and a controller coupled with the semiconductor storage device via an input/output pad and configured to control the semiconductor storage device. The semiconductor storage device includes a first semiconductor structure including a substrate a