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EP-4742850-A2 - THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME

EP4742850A2EP 4742850 A2EP4742850 A2EP 4742850A2EP-4742850-A2

Abstract

Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Inventors

  • WU, JIANZHONG
  • XU, Zongke
  • GENG, JINGJING

Assignees

  • Yangtze Memory Technologies Co., Ltd.

Dates

Publication Date
20260513
Application Date
20200424

Claims (15)

  1. A three- dimensional (3D) memory device, comprising: a core region comprising: channel structures extending through a stack structure (604) along a vertical direction; and a first top-select-gate, (TSG,) cut structure (610) extending along a first direction and extending through a portion of the channel structures, wherein the first direction is perpendicular to the vertical direction; a staircase region comprising: a first support structure (126) extending through the stack structure along the vertical direction; and a second top-select-gate, (TSG,) cut structure (612, 112) extending along the first direction and extending through a portion of the first support structure(126), wherein the second TSG cut structure (612) is aligned with the first TSG cut structure (610) along the first direction.
  2. The 3D memory device of claim 1, further comprising source contact structures (124) extending through the stack structure (104) along the vertical direction, wherein the source contact structures (124) extend along the first direction and are arranged along a second direction perpendicular to the first direction; wherein the first TSG cut structure (610, 110) is between adjacent source contact structures (124) along the second direction, and the second TSG cut structure (612, 112) is between adjacent source contact structures (124) along the second direction.
  3. The 3D memory device of claim 1, further comprising a second support structure on a side of the second TSG cut structure (612, 112) in a second direction perpendicular to the first direction, wherein the second support structure and the first support structure comprise a same material.
  4. The 3D memory device of claim 1, wherein the first support structure has a dimension along the first direction greater than a dimension along a second direction perpendicular to the first direction.
  5. The 3D memory device of claim 1, wherein along a second direction perpendicular to the first direction, a dimension of the first support structure is greater than a dimension of the second TSG cut structure.
  6. The 3D memory device of claim 5, wherein the first support structure protrudes from both sides of the second DSG cut structure along the second direction.
  7. The 3D memory device of claim 1, wherein along a lateral plane, the first support structure has an oval shape or a rectangular shape.
  8. The 3D memory device of claim 1, wherein the first TSG cut structure and the second TSG cut structure comprise at least one of silicon oxide or silicon oxynitride.
  9. The 3D memory device of claim 3, wherein the first support structure and the second support structure comprise at least one of silicon oxide or silicon oxynitride.
  10. The 3D memory device of claim 1, wherein the first TSG cut structure is formed by a process comprising replacing a portion of the channel structures and the stack structure (604) with a dielectric material, the second TSG cut structure is formed by a process comprising replacing a portion of the first support structure and the stack structure (604) with a dielectric material.
  11. The 3D memory device of claim 1, wherein the channel structures comprise first channel structures, the first channel structures being dummy channel structures (116), and second channel structures (117), the first channel structures are aligned with the first TSG cut structure (610, 110) in the vertical direction, and the second channel structures are outside of the first TSG cut structure (610, 110).
  12. The 3D memory device of claim 11, wherein the first channel structures (116) and second channel structures (117) are formed in a same process, the first channel structures being dummy channel structures.
  13. A method for forming a three-dimensional, (3D,) memory device (200), comprising: forming a dielectric stack (304) comprising first/second dielectric layer pairs; forming channel structures (617) extending through the dielectric stack (304) along a vertical direction (z) in a core region of the dielectric stack (304); removing a portion of at least one of the channel structures (617) and a portion of the dielectric stack (304) to form a first top-select-gate, (TSG,) cut opening (615) in the core region, wherein the first TSG cut opening (615) extends along the vertical direction (z) and a first direction (x) perpendicular to the vertical direction (z); forming a first top-select-gate, (TSG,) cut structure (610) in the first TSG cut opening; forming, in a same process that forms the first TSG cut opening, a second top-select-gate, (TSG,) cut opening in a staircase region, wherein the second TSG cut opening extends along the vertical direction (z) and the first direction (x); and forming a second top-select-gate, (TSG,) cut structure (612) in the second TSG cut opening, wherein the second TSG cut structure (612) is aligned with the first TSG cut structure (610) along the first direction (x); and forming a first support structure (126) extending through the dielectric stack (304) along the vertical direction, wherein the second TSG cut structure (612) extends through a portion of the first support structure (126).
  14. The method of claim 13, wherein the forming a first support structure (126) extending through the dielectric stack (304) along the vertical direction comprise: forming, in a different process that forms the second TSG cut opening, support openings extending along the vertical direction (z) in the staircase region; forming the first support structure (126) in the support openings.
  15. The method of claim 13, further comprising: forming a staircase structure in the staircase region of the dielectric stack (304); wherein the first TSG cut opening and the second TSG cut opening are formed after a formation of the staircase structure.

Description

Technical Field Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for forming the 3D memory devices with drain-select-gate (DSG) cut structures. BACKGROUND Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. SUMMARY Embodiments of 3D memory devices and methods for forming the 3D memory devices with DSG cut structures are provided. In one example, a 3D memory device includes a core region and a staircase region having a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction, the staircase region. The staircase region includes a DSG cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction. In another example, a method for forming a 3D memory device includes the following operations. First, a dielectric stack having a plurality of first/second dielectric layer pairs over a substrate is formed. A DSG cut opening is formed in a core region of the dielectric stack. A staircase structure having a plurality of stairs is formed extending along a lateral direction in a staircase region of the dielectric stack. In a different process than the DSG cut opening, a second DSG cut opening is formed in the staircase region and extending along the lateral direction. A DSG cut structure is formed in the DSG cut opening and a second DSG cut structure is formed in the second DSG cut opening. In a further example, a method for forming a 3D memory device includes the following operations. First, a dielectric stack having a plurality of first/second dielectric layer pairs is formed over a substrate. A channel structure is formed in a core region of the dielectric stack. A staircase structure is formed having a plurality of stairs extending along a lateral direction in a staircase region of the dielectric stack. In a same process, a DSG cut opening is formed in a core region of the dielectric stack and a second DSG cut opening is formed in a staircase region of the dielectric stack. A DSG cut structure is formed in the DSG cut opening and a second DSG cut structure is formed in the second DSG cut opening. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. FIG. 1A illustrates a cross-sectional view of an exemplary 3D memory device, according to some embodiments of the present disclosure.FIG. 1B illustrates a cross-sectional view of another exemplary 3D memory device, according to some embodiments of the present disclosure.FIG. 1C illustrates a top view of the exemplary 3D memory devices shown in FIGs. 1A and 1B, according to some embodiments of the present disclosure.FIG. 2A illustrates a cross-sectional view of another exemplary 3D memory device, according to some embodiments of the present disclosure.FIG. 2B illustrates a top view of the exemplary 3D memory device shown in FIG. 2A, according to some embodiments of the present disclosure.FIG. 3 illustrates a cross-sectional view of a 3D memory device formed by an exemplary fabrication process, according to some embodiments of the present disclosure.FIGs. 4A-4D illustrates cross-sectional views of a 3D memory device at various stages of another exemplary fabrication process, according to some embodiments of the present disclosure.FIGs. 5A-5D illustrates cross-sectional views of another 3D memory device at various stages of another exemplary fabrication process, according to some embodiments of the present disclosure.FIGs. 6A-6D illustrates cross-sectional views of another 3D memory device at various stages of another exemplary fabrication process, according to some embodiments of the present disclosure.FIG. 7 illustrates a flowchart of exemplary fabrication operations shown in FIGs. 3 and 4A-4D, according to some embodiments of the present disclosure.FIG. 8 illustrates a flowchart of exemplary fabrication operations shown in FIGs. 3, and 5A-5D, according to some embod