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EP-4742851-A2 - THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

EP4742851A2EP 4742851 A2EP4742851 A2EP 4742851A2EP-4742851-A2

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Inventors

  • WANG, YANHONG
  • LIU, WEI
  • CHEN, LIANG
  • XIA, ZHILIANG
  • ZHOU, WENXI
  • ZHANG, KUN
  • YANG, Yuancheng

Assignees

  • Yangtze Memory Technologies Co., Ltd.

Dates

Publication Date
20260513
Application Date
20210630

Claims (15)

  1. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising: a first semiconductor layer; a first peripheral circuit in contact with the first semiconductor layer, the first peripheral circuit comprising a first transistor; an array of memory cells; a polysilicon layer between the array of memory cells and the first peripheral circuit; a second semiconductor structure comprising: a second semiconductor layer; a second peripheral circuit in contact with the second semiconductor layer, the second peripheral circuit comprising a second transistor; and a bonding interface between the array of memory cells and the second peripheral circuit; and one or more contacts extending vertically through the polysilicon layer.
  2. The 3D memory device of claim 1, further comprising: a first interconnect layer comprising first interconnects coupled to the first peripheral circuit, wherein the first interconnect layer is between the array of memory cells and the first peripheral circuit; a second interconnect layer comprising second interconnects coupled to the array of memory cells; and a third interconnect layer comprising third interconnects coupled to the second peripheral circuit, wherein the second and third interconnect layer are between the array of memory cells and the second peripheral circuit.
  3. The 3D memory device of claim 1 or 2, further a first contact of the one or more contacts comprises a via surrounded by a dielectric spacer to electrically separate the via from polysilicon layer.
  4. The 3D memory device of claim 2, wherein the first contact couples the second interconnects to the first interconnects to make an electrical connection through the polysilicon layer.
  5. The 3D memory device any one of claims 1-4, wherein the array of memory cells comprises an array of NAND memory strings; and the polysilicon layer is in contact with sources of the array of NAND memory strings.
  6. The 3D memory device any one of claims 1-5, wherein the first and second semiconductor layers have different thicknesses.
  7. The 3D memory device of any one of claims 1-6, wherein the first transistor comprises a first gate dielectric; the second transistor comprises a second gate dielectric; and the first and second gate dielectrics have different thicknesses.
  8. The 3D memory device of any one of claims 1-7, further comprising a third peripheral circuit in contact with the first semiconductor layer, the third peripheral circuit comprising a third transistor comprising a third gate dielectric; and a fourth peripheral circuit in contact with the second semiconductor layer, the fourth peripheral circuit comprising a fourth transistor comprising a fourth gate dielectric, wherein the third and fourth peripheral circuits comprise at least one of a page buffer circuit or a logic circuit.
  9. The 3D memory device of any one of claims 1-8, wherein the first peripheral circuit comprises a driving circuit, and the second peripheral circuit comprises an input/output (I/O) circuit, or vice versa.
  10. The 3D memory device of any one of claims 1-9, further comprising: a fourth interconnect layer comprising fourth interconnects, wherein the first interconnect layer and the fourth interconnect layer are formed on opposite sides of the first semiconductor layer.
  11. The 3D memory device of claims 10, further comprising: a second contact extending vertically through the first semiconductor layer and coupled to the fourth interconnects and the first interconnects.
  12. The 3D memory device of claims 10, wherein the fourth interconnects formed in one or more ILD layers.
  13. The 3D memory device of any one of claims 1-12, further comprising: a first voltage source coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; and a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit, wherein the first voltage is different from the second voltage.
  14. The 3D memory device of any one of claims 1-13, further comprising: a first bonding layer comprising a first bonding contact; and a second bonding layer comprising a second bonding contact; and wherein the first bonding contact is in contact with the second bonding contact at the bonding interface.
  15. A system, comprising: a memory device according to any one of claims 1 to 14 configured to store data; and a memory controller coupled to the memory device and configured to control the array of memory cells through the first peripheral circuit and the second peripheral circuit.

Description

BACKGROUND The present disclosure relates to memory devices. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. SUMMARY In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The system also includes a memory controller coupled to the memory device and configured to control the array of memory cells through the first peripheral circuit and the second peripheral circuit. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. FIG. 1A illustrates a schematic view of a cross-section of a 3D memory device, according to some aspects of the present disclosure.FIG. 1B illustrates a schematic view of a cross-section of another 3D memory device, according to some aspects of the present disclosure.FIG. 2 illustrates a schematic circuit diagram of a memory device including peripheral circuits, according to some aspects of the present disclosure.FIG. 3 illustrates a block diagram of a memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.FIG. 4A illustrates a block diagram of peripheral circuits provided with various voltages, according to some aspects of the present disclosure.FIG. 4B illustrates a schematic diagram of peripheral circuits provided with various voltages arranged in separate semiconductor structures, according to some aspects of the present disclosure.FIGs. 5A and 5B illustrate a perspective view and a side view, respectively, of a planar transistor, according to some aspects of the present disclosure.FIGs. 6A and 6B illustrate a perspective view and a side view, respectively, of a 3D transistor, according to some aspects of the present disclosure.FIG. 7 illustrates a circuit diagram of a word line driver and a page buffer, according to some aspects of the present disclosure.FIG. 8 illustrates a side view of a NAND memory string in 3D memory devices, according to some aspects of the present disclosure.FIGs. 9A and 9B illustrate schematic views of cross-sections of 3D memory devices having two stacked semiconductor structures, according to various aspects of the present disclosure.FIG. 10 illustrates a schematic view of a cross-section of the 3D memory devices in FIGs. 9A and 9B, according to various aspects of the present disclosure.FIGs. 11A and 11B illustrate side views of various examples of the 3D memory device in FIG. 10, according to various aspects of the present disclosure.FIGs. 12A-12G illustrate a fabrication process for forming the 3D memory device in FIG. 10, according to some aspects of the present disclosure.FIGs. 13A and 13B illustrate another fabrication process for forming the 3D memory devices in FIG. 10, according to some aspects of the present disclosure.FIG. 14 illustrates a flowchart of a method for forming the 3D memory device in FIG. 10, according to some aspects of the present disclo