EP-4742854-A2 - GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH SUBSTRATE CONNECTION PORTIONS

Abstract

Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure comprises: a sub-fin; a vertical arrangement of nanowires over the sub-fin; a first source or drain structure at a first end of the vertical arrangement of nanowires; a second source or drain structure at a second end of the vertical arrangement of nanowires; a gate stack over and around each of the nanowires of the vertical arrangement of nanowires and laterally between the first source or drain structure and the second source or drain structure; a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.

Inventors

• HASAN, MOHAMMAD
• CEA, STEPHEN M.
• JAHAGIRDAR, ANANT H.
• KUMAR, NITESH
• Shah, Rushabh
• MURTHY, ANAND S.
• PATEL, PRATIK
• GHANI, TAHIR
• MEYER, TRICIA
• BOMBERGER, Cory
• GLASS, GLENN A.

Assignees

• INTEL Corporation

Dates

Publication Date

20260513

Application Date

20221012

Claims (7)

1. An integrated circuit structure, comprising: a sub-fin; a vertical arrangement of nanowires over the sub-fin; a first source or drain structure at a first end of the vertical arrangement of nanowires, the first source or drain structure having an upper portion and a lower epitaxial extension portion, wherein the upper portion of the first source or drain structure has a lateral width greater than a lateral width of the lower epitaxial extension portion of the first source or drain structure; a second source or drain structure at a second end of the vertical arrangement of nanowires, the second end laterally opposite the first end, the second source or drain structure having an upper portion and a lower epitaxial extension portion, wherein the upper portion of the second source or drain structure has a lateral width greater than a lateral width of the lower epitaxial extension portion of the second source or drain structure; a gate stack over and around each of the nanowires of the vertical arrangement of nanowires and laterally between the first source or drain structure and the second source or drain structure; a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.
2. The integrated circuit structure of claim 1, wherein the vertical arrangement of nanowires comprises a first nanowire, a second nanowire over the first nanowire, and a third nanowire over the second nanowire.
3. The integrated circuit structure of claim 1 or 2, wherein the first conductive contact has an uppermost surface at a same level as an uppermost surface of the gate stack.
4. The integrated circuit structure of claim 3, wherein the second conductive contact has an uppermost surface at a same level as the uppermost surface of the gate stack.
5. The integrated circuit structure of any one of claims 1 to 4, wherein the vertical arrangement of nanowires is a vertical arrangement of silicon nanowires.
6. The integrated circuit structure of any one of claims 1 to 5, wherein the lower epitaxial extension portion of the first source or drain structure laterally adjacent to the sub-fin, wherein the lateral width of the upper portion of the first source or drain structure along a source to drain direction is greater than the lateral width of the lower epitaxial extension portion of the first source or drain structure along the source to drain direction, and wherein the upper portion of the first source or drain structure has an outermost sidewall at the first end of the vertical arrangement of nanowires.
7. The integrated circuit structure of claim 6, wherein the lower epitaxial extension portion of the second source or drain structure laterally adjacent to the sub-fin, wherein the lateral width of the upper portion of the second source or drain structure along the source to drain direction is greater than the lateral width of the lower epitaxial extension portion of the second source or drain structure along the source to drain direction, and wherein the upper portion of the second source or drain structure has an outermost sidewall at the second end of the vertical arrangement of nanowires.

Description

TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Nanowires used to fabricate devices provide improved short channel control. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a cross-sectional view representing a gate-all-around integrated circuit structure having source or drain structures with substrate connection portions, in accordance with an embodiment of the present disclosure.Figures 2A-2E illustrate cross-sectional views representing various operations in an method of fabricating a gate-all-around integrated circuit structure having source or drain structures with substrate connection portions, in accordance with an embodiment of the present disclosure.Figures 3A-3H illustrate cross-sectional views representing various operations in an method of fabricating a gate-all-around integrated circuit structure using an implanted surfactant catalyst, in accordance with an embodiment of the present disclosure.Figure 4 illustrates a cross-sectional view representing various a gate-all-around integrated circuit structure fabricated using an implanted surfactant catalyst, in accordance with an embodiment of the present disclosure.Figure 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure.Figure 6 illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure.Figure 7 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure.Figure 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A, as taken along the a-a' axis, in accordance with an embodiment of the present disclosure.Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 8A, as taken along the b-b' axis, in accordance with an embodiment of the present disclosure.Figure 9 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure.Figure 10 illustrates an interposer that includes one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS Gate-all-around integrated circuit structures having source or drain structures with substrate connection porti