EP-4742856-A2 - METHOD FOR MANUFACTURING A QUANTUM ELECTRONIC CIRCUIT WITH REDUCED GATE PITCH

Abstract

One aspect of the invention relates to an electronic circuit (1) comprising on a substrate: • the first electrodes (51) distributed according to a constant pitch R: • second electrodes (52), each arranged between two adjacent first electrodes, • third grid electrodes (53), each disposed between a first electrode and a second electrode located next to each other, in which the first, second and third electrodes are distributed according to an average pitch equal to R/4, and in which at least two electrodes among the first electrodes or at least two electrodes among the second electrodes or at least two grid electrodes among the third electrodes, each have an electrical contact independent of each other.

Inventors

• NIEBOJEWSKI, HEIMANU

Assignees

• Commissariat à l'Energie Atomique et aux Energies Alternatives

Dates

Publication Date

20260513

Application Date

20241105

Claims (9)

1. Electronic circuit (1) comprising, on a substrate: - first grid electrodes (51) spaced apart from each other, each first grid electrode (51) having a first branch (51a) extending parallel to a first direction (X), the first branches (51a) of the first grid electrodes being distributed according to a constant pitch R, measured along a second direction (Y) perpendicular to the first direction; - second grid electrodes (52), each second grid electrode being disposed between two adjacent first grid electrodes, each second grid electrode (52) having a first branch (52a) extending between the first two branches (51a) of the adjacent first grid electrodes (51), The electronic circuit is characterized in that it comprises third gate electrodes (53), each third gate electrode (53) being disposed between a first gate electrode (51) and a second gate electrode (52) adjacent to each other, each third gate electrode (52) having a first branch (53a) extending between a first branch (51a) of a first gate electrode (51) and a first branch (52a) of a second gate electrode (52), and in that the first, second, and third gate electrodes (51, 52, 53) are distributed according to an average pitch, measured along the second direction (Y), equal to R/4, the first, second, and third gate electrodes (51, 52, 53) extending at least partially over a portion (2) of the substrate (4), called the "active zone," configured to accommodate quantum dots, at least two gate electrodes grid among the first grid electrodes or at least two grid electrodes among the second grid electrodes or at least two grid electrodes among the third grid electrodes, each have an electrical contact independent of each other.
2. Electronic circuit (1) according to claim 1, wherein the first grid electrodes (51) comprise a first conductive material, the second grid electrodes (52) comprise a second conductive material, identical to the first conductive material, and the third grid electrodes (53) include a third conductive material, identical to the materials of the first and second grid electrodes (51, 52).
3. Electronic circuit (1) according to any one of the preceding claims, wherein each third grid electrode (53) has a portion (53c, 53d), referred to as the "free portion", extending beyond the first and second grid electrodes (51, 52), the electronic circuit (1) comprising electrical contacts (9), each electrical contact being connected to a free portion (53c, 53d) of a third grid electrode (53) extending beyond the first and second grid electrodes (51, 52).
4. Electronic circuit (1) according to any one of the preceding claims, wherein each of the first, second and third grid electrodes (51, 52, 53) comprises a second branch (51b, 52b, 53b) extending perpendicularly to its first branch (51a, 52a, 53a).
5. Electronic circuit (1) according to any one of the preceding claims, wherein each of the second and third grid electrodes (52, 53) which fit between the first grid electrodes (51) has a second portion extending along the second direction (Y).
6. Electronic circuit (1) according to any one of the preceding claims, wherein at least two grid electrodes among the first grid electrodes (51) or at least two grid electrodes among the second grid electrodes (52) or at least two grid electrodes among the third grid electrodes (53) are independently polarized.
7. Electronic circuit (1) according to any one of the preceding claims, wherein the active area (2) comprises a semiconductor thin layer (21), intended to receive the quantum dots, and an insulating layer (22) extending over the semiconductor thin layer (21) between the semiconductor thin layer (21) and the first, second and third gate electrodes (51, 52, 53).
8. Electronic circuit (1) according to any one of the preceding claims, wherein each of the first grid electrodes (51) has a flank (510), said flank (510) being a lateral surface delimiting said first grid electrode (51).
9. Electronic circuit (1) according to any one of the preceding claims, wherein the first, second and third grid electrodes (51, 52, 53) are separated from each other by an insulating film (31).

Description

TECHNICAL FIELD OF THE INVENTION The technical field of the invention is that of quantum electronics and more particularly the manufacture of such a circuit. TECHNOLOGICAL BACKGROUND OF THE INVENTION The manipulation of quantum states, also called "qubits" (short for "quantum bits"), offers new possibilities in information manipulation. There are several types of qubits, such as spin qubits, for which information is stored in the quantum state of a spin. Quantum electronic circuits capable of manipulating spin qubits include islands, also called quantum dots, which can store qubits for the duration of their manipulation and measurement. There Fig. 1 This represents a simplified example of a commonly implemented AA1 electronic circuit architecture. According to this architecture, AA21 quantum dots are formed within a semiconducting layer AA11, known as the qubit layer. The AA21 dots correspond to wells formed in the electrostatic potential AA20 of the AA11 qubit layer by means of conductive electrodes AA13, called "gate electrodes" or "gates." The AA13 gates are arranged on the AA11 qubit layer and electrically isolated from it by a dielectric layer AA12, called "gate oxide" because it is frequently formed by an oxide. Modulating the electrical potential of the AA13 gates allows the shape of the AA21 quantum dots to be modulated. When each AA21 dot contains an A2 qubit, these modulations allow the manipulation of the AA2 qubits. The integration of AA21 quantum dots into electronic circuits must meet several requirements. Firstly, it must offer high integration density to provide significant computing power. Secondly, the fabrication processes for these quantum electronic circuits must ensure low circuit variability. Indeed, the efficiency of storing and manipulating AA2 qubits is heavily dependent on the position of the qubits within the AA21 quantum dots. However, these can be influenced by their environment. There Fig. 2 considers the circuit of the Fig. 1 in which an AA14 charge distribution is dispersed within the AA11 qubit layer and/or the AA12 dielectric layer. These AA14 charges correspond, for example, to dopants or diluted vacancies within these AA11 and AA12 layers. This AA14 charge distribution modifies the AA20 electrostatic potential at the AA11 qubit layer and distorts the AA21 quantum dots. Parasitic AA21' potential wells can form, trapping the AA2 qubits. The AA2 qubits thus become erratically located instead of being aligned with the AA13 grids. Manipulating the AA2 qubits becomes more difficult. To reduce the impact of AA14 electrical charges on the localization of qubits 2, it is known to reduce the spacing between neighboring AA13 grids. Reducing the spacing between these AA13 grids is equivalent to reducing the distribution interval between these AA13 grids, called the pitch. A grid pitch of less than 80 nm, and preferably less than 25 nm, effectively counteracts the impact of the AA14 electrical charge distribution on the AA21 boxes. However, fabricating an electronic circuit with a significantly reduced grid pitch raises new challenges. The fabrication of AA13 grids with a pitch smaller than 25 nm, for example, requires the implementation of extreme ultraviolet (EUV) lithography steps. This type of lithography requires expensive and complex equipment. Furthermore, it can lead to pitch walking when several EUV lithography steps are performed consecutively. A small grid pitch also complicates the alignment of electrical contacts on each grid. Misalignment or contact overflow can short-circuit multiple grids, rendering the circuit unusable. The document US 2019/0140073 A1 describes a process for fabricating a quantum device from a substrate onto which initial grids are laid. These initial grids are arranged parallel to each other and according to an initial grid pitch. Secondary grids are formed between the initial grids. The first and second grids are thus distributed with a reduced pitch, equal to half the initial grid pitch. This process reduces the final grid pitch of the quantum circuit. However, unless EUV lithography steps are implemented, it does not allow for a final pitch small enough to improve qubit localization. SUMMARY OF THE INVENTION There is therefore a need to provide an electronic circuit that can form quantum dots of reduced width, for example less than 80 nm, and which does not require the implementation of EUV lithography steps for its fabrication. The invention provides a method for manufacturing an electronic circuit that achieves a final grid pitch four times smaller than the initial grid pitch, for example, equal to the minimum pitch achievable with DUV (Deep UV) lithography equipment. It is thus possible to achieve a final grid pitch of less than 80 nm, or even less than 25 nm, with DUV equipment that typically achieves a grid pitch of 100 nm. To this end, the invention relates to a method for manufacturing an electronic circuit from a substrate, comprising t