EP-4742857-A2 - INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS WITH MATCHED WORK FUNCTION SCHEME AND METHODS OF FABRICATION THE SAME

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first transistor on a substrate; and a second transistor on the first transistor, wherein the first transistor is between the substrate and the second transistor in a vertical direction that is perpendicular to an upper surface of the substrate, wherein the first transistor comprises: first channel layers that are spaced apart from each other in the vertical direction; and a first work function layer on the first channel layers, wherein the second transistor comprises: second channel layers that are spaced apart from each other in the vertical direction; and a second work function layer on the second channel layers, and wherein the second work function layer is spaced apart from the first channel layers.

Inventors

• Park, Junmo
• SEO, KANG-ILL

Assignees

• Samsung Electronics Co., Ltd.

Dates

Publication Date

20260513

Application Date

20251022

Claims (14)

1. An integrated circuit device comprising: a first transistor on a substrate; and a second transistor on the first transistor, wherein the first transistor is between the substrate and the second transistor in a vertical direction that is perpendicular to an upper surface of the substrate, wherein the first transistor comprises: first channel layers that are spaced apart from each other in the vertical direction; and a first work function layer on the first channel layers, wherein the second transistor comprises: second channel layers that are spaced apart from each other in the vertical direction; and a second work function layer on the second channel layers, and wherein the second work function layer is spaced apart from the first channel layers.
2. The integrated circuit device of Claim 1, wherein the first work function layer is between the first channel layers and the second work function layer.
3. The integrated circuit device of Claim 2, wherein the second work function layer includes a second inner work function layer and a second outer work function layer, wherein the second inner work function layer is between adjacent ones of the second channel layers, wherein the second outer work function layer extends around the second channel layers and the second inner work function layer, and wherein the second work function layer has an interface between the second inner work function layer and the second outer work function layer.
4. The integrated circuit device of Claim 3, wherein the first work function layer includes a first inner work function layer and a first outer work function layer, wherein the first inner work function layer is between adjacent ones of the first channel layers, wherein the first outer work function layer extends around the first channel layers and the first inner work function layer, and wherein the first work function layer is free of an interface between the first inner work function layer and the first outer work function layer.
5. The integrated circuit device of Claim 4, wherein the first inner work function layer and the first outer work function layer are configured to form an integrated structure.
6. The integrated circuit device of Claim 4 or 5, wherein the interface of the second work function layer overlaps the second channel layers in the vertical direction.
7. The integrated circuit device of Claim 6, wherein a width of at least one of the second channel layers in a horizontal direction that is parallel with the upper surface of the substrate is greater than a width of the second inner work function layer in the horizontal direction.
8. The integrated circuit device of any one of Claims 4 to 7, wherein the first inner work function layer and the first outer work function layer include a first material.
9. The integrated circuit device of Claim 8, wherein the second inner work function layer and the second outer work function layer include a second material that is different from the first material.
10. The integrated circuit device of Claim 8, wherein the second inner work function layer includes a second material, wherein the second outer work function layer includes a third material, and wherein the second material is different from the first material and the third material.
11. A method of forming an integrated circuit device, the method comprising: forming a first stack that comprises first channel layers on a substrate and a second stack that comprises second channel layers on the first stack, wherein the first channel layers are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate, and the second channel layers are spaced apart from each other in the vertical direction; forming an insulator between the first stack and the second stack in the vertical direction; forming a dummy layer that extends around the first channel layers, the second channel layers, and the insulator; replacing an upper portion of the dummy layer with a first inner work function layer that is on the second channel layers; replacing a lower portion of the dummy layer with a second work function layer that is on the first channel layers; and forming a first outer work function layer on the first inner work function layer, the insulator, and the second work function layer, wherein the first outer work function layer is spaced apart from the first channel layers by the second work function layer.
12. The method of Claim 11, wherein the first outer work function layer is in contact with the first inner work function layer.
13. The method of Claim 12, wherein the integrated circuit device includes an interface between the first outer work function layer and the first inner work function layer.
14. The method of Claim 13, wherein the first outer work function layer and the first inner work function layer include a first material, and wherein the second work function layer includes a second material that is different from the first material.

Description

BACKGROUND The present disclosure generally relates to the field of integrated circuit devices and, more particularly, to integrated circuit devices including stacked transistors. Various structures of an integrated circuit device and methods of forming the same have been proposed to increase the integration density. For example, a stacked transistor structure including multiple transistors vertically stacked has been proposed. SUMMARY An aspect of the present disclosure is to provide integrated circuit devices with improved electrical characteristics and reliability characteristics, and methods for manufacturing the same. More specifically, an aspect of the present disclosure is to provide integrated circuit devices, including a stacked transistor structure comprising multiple transistors and matched work function layers therefor to improve and optimize the performance. However, it will be understood that the embodiments, goals, and benefits of the present disclosure are not limited to the descriptions above. An integrated circuit device, according to some embodiments, may include a first transistor on a substrate; and a second transistor on the first transistor, wherein the first transistor is between the substrate and the second transistor in a vertical direction that is perpendicular to an upper surface of the substrate, wherein the first transistor comprises: first channel layers that are spaced apart from each other in the vertical direction; and a first work function layer on the first channel layers, wherein the second transistor comprises: second channel layers that are spaced apart from each other in the vertical direction; and a second work function layer on the second channel layers, and wherein the second work function layer is spaced apart from the first channel layers. An integrated circuit device, according to some embodiments, may include a first transistor on a substrate; a second transistor on the first transistor; and an insulator between the first transistor and the second transistor in a vertical direction that is perpendicular to an upper surface of the substrate, wherein the first transistor comprises: first channel layers that are spaced apart from each other in the vertical direction; and a first work function layer on the first channel layers, wherein the second transistor comprises: second channel layers that are spaced apart from each other in the vertical direction; and a second work function layer on the second channel layers, and wherein the second work function layer is spaced apart from the first channel layers by the first work function layer. A method of forming an integrated circuit device, according to some embodiments, may include forming a first stack that comprises first channel layers on a substrate and a second stack that comprises second channel layers on the first stack, wherein the first channel layers are spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate, and the second channel layers are spaced apart from each other in the vertical direction; forming an insulator between the first stack and the second stack in the vertical direction; forming a dummy layer that extends around the first channel layers, the second channel layers, and the insulator; replacing an upper portion of the dummy layer with a first inner work function layer that is on the second channel layers; replacing a lower portion of the dummy layer with a second work function layer that is on the first channel layers; and forming a first outer work function layer on the first inner work function layer, the insulator, and the second work function layer, wherein the first outer work function layer is spaced apart from the first channel layers by the second work function layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an integrated circuit device according to some embodiments.FIG. 2 is a flowchart of methods of forming an integrated circuit device according to some embodiments.FIGS. 3 through 19 are cross-sectional views illustrating methods of forming an integrated circuit device according to some embodiments.FIG. 3 is a cross-sectional view of an intermediate process, including forming an inter-gate sacrificial layer on a stack.FIG. 4 is a cross-sectional view of an intermediate process, including removing a portion of the inter-gate sacrificial layer and a portion of the stack.FIGS. 5 and 6 are cross-sectional views of an intermediate process, including replacing the inter-gate sacrificial layer with an insulator.FIG. 7 is a cross-sectional view of an intermediate process, including removing sacrificial layers.FIG. 8 is a cross-sectional view of an intermediate process, including forming a dummy layer.FIG. 9 is a cross-sectional view of an intermediate process, including removing an outer dummy layer.FIG. 10 is a cross-sectional view of an intermediate process, including forming a block layer.FIG. 11 is a cro