EP-4742868-A1 - DISPLAY PANEL AND DISPLAY APPARATUS

EP4742868A1EP 4742868 A1EP4742868 A1EP 4742868A1EP-4742868-A1

Abstract

Embodiments of the present disclosure provides a display panel and a display device, the display panel comprising a first type of pixel and a second type of pixel, The first type of pixel comprises a first sub-pixel of a first color, and the second type of pixel comprises a second sub-pixel of the first color. The display panel further comprises a base plate, a device layer, and a light modulation layer. The device layer is disposed on a side of the substrate, and the light modulation layer is located on a side of the device layer away from the substrate. The light modulation layer comprises a plurality of light modulation portions. The first sub-pixel has a first orthographic projection on the base plate, and the second sub-pixel has a second orthographic projection on the base plate. The orthographic projection of the light modulation portion on the base plate at least partially overlaps with the first orthographic projection. A ratio of a perimeter to an area corresponding to the first orthographic projection is greater than a ratio of a perimeter to an area corresponding to the second orthographic projection. In the embodiments of the present disclosure, the anti-peeping effect corresponding to the first sub-pixel can be improved.

Inventors

DAI, Hao
Ma, Yangzhao
ZHANG, Dian
DUN, DONGLIANG
LIN, Yuancheng
HUA, Huomei

Assignees

Wuhan Tianma Microelectronics Co., Ltd.
Xiamen Tianma Display Technology Co., Ltd.

Dates

Publication Date: 20260513
Application Date: 20240925

Claims (20)

A display panel, comprising a display region, wherein the display region comprises a plurality of pixel circuits arranged in an array, the plurality of pixel circuits comprising a first pixel circuit, a second pixel circuit and a third pixel circuit; the first pixel circuit, the second pixel circuit and the third pixel circuit being respectively connected to light-emitting elements of different colors; the display panel further comprising a plurality of data signal lines, the plurality of data signal lines comprising a first data signal line, a second data signal line and a third data signal line; the first data signal line being electrically connected to the first pixel circuit, the second data signal line being electrically connected to the second pixel circuit, and the third data signal line being electrically connected to the third pixel circuit.
The display panel according to claim 1, wherein the plurality of pixel circuits form a plurality of first pixel circuit columns, the first pixel circuit column comprising the first pixel circuits and the second pixel circuits alternately arranged along a column direction; the plurality of pixel circuits form a plurality of second pixel circuit columns, the second pixel circuit column comprising the third pixel circuits arranged along the column direction; the first pixel circuit columns and the second pixel circuit columns are alternately arranged along a row direction; a plurality of the data signal lines extend along the column direction and are arranged along the row direction; the first data signal line is electrically connected to the first pixel circuits in a same first pixel circuit column, the second data signal line is electrically connected to the second pixel circuits in a same first pixel circuit column, and the third data signal line is electrically connected to the third pixel circuits in a same second pixel circuit column.
The display panel according to claim 2, wherein the plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, the first pixel circuit column group comprising two first pixel circuit columns which are respectively a first intra-group pixel circuit column and a second intra-group pixel circuit column; the first data signal line connected to the first pixel circuits in the first intra-group pixel circuit column is a first intra-group data signal line; the second data signal line connected to the second pixel circuits in the first intra-group pixel circuit column is a second intra-group data signal line; the first data signal line connected to the first pixel circuits in the second intra-group pixel circuit column is a third intra-group data signal line; the second data signal line connected to the second pixel circuits in the second intra-group pixel circuit column is a fourth intra-group data signal line; in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line, and the second intra-group data signal line is electrically connected to the fourth intra-group data signal line; the first pixel circuit connected to the first intra-group data signal line is located in different pixel circuit rows from the first pixel circuit connected to the third intra-group data signal line, and the second pixel circuit connected to the second intra-group data signal line is located in different pixel circuit rows from the second pixel circuit connected to the fourth intra-group data signal line.
The display panel according to claim 3, wherein the first pixel circuits and the second pixel circuits are arranged alternately at intervals along the row direction; the first pixel circuit column group comprises two adjacent first pixel circuit columns.
The display panel according to claim 3, further comprising a non-display region located at least on one side of the display region; wherein in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line via a first data connecting line; the second intra-group data signal line is electrically connected to the fourth intra-group data signal line via a second data connecting line; and the first data connecting line and the second data connecting line are both located in the non-display region.
The display panel according to claim 3, wherein in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line via a first data connecting line; the second intra-group data signal line is electrically connected to the fourth intra-group data signal line via a second data connecting line; and the first data connecting line and the second data connecting line are both located in the display region.
The display panel according to claim 3, further comprising a plurality of data signal output lines and a plurality of gating circuits; wherein the data signal output lines comprise a first data signal output line and a second data signal output line; the gating circuits comprise a first gating circuit and a second gating circuit; in the first pixel circuit column group, the first intra-group data signal line and the third intra-group data signal line are electrically connected to a same first data signal output line via the first gating circuit, the first gating circuit being configured to transmit a data signal output by the first data signal output line to the first intra-group data signal line and the third intra-group data signal line in a time-division manner; in the first pixel circuit column group, the second intra-group data signal line and the fourth intra-group data signal line are electrically connected to a same second data signal output line via the second gating circuit, the second gating circuit is configured to transmit a data signal output by the second data signal output line to the second intra-group data signal line and the fourth intra-group data signal line in a time-division manner.
The display panel according to claim 7, wherein the first gating circuit comprises a first switching transistor and a second switching transistor, the first switching transistor being connected between the first intra-group data signal line and the first data signal output line, and the second switching transistor being connected between the third intra-group data signal line and the first data signal output line; the second gating circuit comprises a third switching transistor and a fourth switching transistor, the third switching transistor being connected between the second intra-group data signal line and the second data signal output line, and the fourth switching transistor being connected between the fourth intra-group data signal line and the second data signal output line; and a gate of the first switching transistor and a gate of the fourth switching transistor are configured to receive a first switching signal; a gate of the second switching transistor and a gate of the third switching transistor are configured to receive a second switching signal.
The display panel according to claim 2, wherein the plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, the first pixel circuit column group comprising two adjacent first pixel circuit columns which are respectively a first intra-group pixel circuit column and a second intra-group pixel circuit column; the first data signal line connected to the first pixel circuits in the first intra-group pixel circuit column is a first intra-group data signal line; the second data signal line connected to the second pixel circuits in the first intra-group pixel circuit column is a second intra-group data signal line; the first data signal line connected to the first pixel circuits in the second intra-group pixel circuit column is a third intra-group data signal line; the first data signal line connected to the second pixel circuits in the second intra-group pixel circuit column is a fourth intra-group data signal line; in the row direction, the first intra-group data signal line and the second intra-group data signal line are located on different sides of the first intra-group pixel circuit column, and the third intra-group data signal line and the fourth intra-group data signal line are located on different sides of the second intra-group pixel circuit column.
The display panel according to claim 2, wherein the plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, the first pixel circuit column group comprising two first pixel circuit columns which are respectively a first intra-group pixel circuit column and a second intra-group pixel circuit column; the first data signal line connected to the first pixel circuits in the first intra-group pixel circuit column is a first intra-group data signal line; the second data signal line connected to the second pixel circuits in the first intra-group pixel circuit column is a second intra-group data signal line; the first data signal line connected to the first pixel circuits in the second intra-group pixel circuit column is a third intra-group data signal line; the second data signal line connected to the second pixel circuits in the second intra-group pixel circuit column is a fourth intra-group data signal line; in the first pixel circuit column group, the second intra-group data signal line and the fourth intra-group data signal line are located between the first intra-group data signal line and the third intra-group data signal line.
The display panel according to claim 10, further comprising a non-display region located at least on one side of the display region; in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line via a first data connecting line; the second intra-group data signal line is electrically connected to the fourth intra-group data signal line via a second data connecting line; the first data connecting line and the second data connecting line are both located in the non-display region; and the second data connecting line is located on a side of the first data connecting line close to the display region.
The display panel according to claim 11, further comprising a plurality of data signal output lines; wherein the data signal output lines comprise a first data signal output line and a second data signal output line; in the first pixel circuit column group, the first data connecting line is electrically connected to the first data signal output line, and the second data connecting line is electrically connected to the second data signal output line; and the first data connecting line and the second data signal output line are located in different layers.
The display panel according to claim 2, wherein the plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, the first pixel circuit column group comprising two first pixel circuit columns which are respectively a first intra-group pixel circuit column and a second intra-group pixel circuit column; the first data signal line connected to the first pixel circuits in the first intra-group pixel circuit column is a first intra-group data signal line; the second data signal line connected to the second pixel circuits in the first intra-group pixel circuit column is a second intra-group data signal line; the first data signal line connected to the first pixel circuits in the second intra-group pixel circuit column is a third intra-group data signal line; the second data signal line connected to the second pixel circuits in the second intra-group pixel circuit column is a fourth intra-group data signal line; in the first pixel circuit column group, the first intra-group data signal lines, the second intra-group data signal lines, the third intra-group data signal lines and the fourth intra-group data signal lines are sequentially arranged along the row direction.
The display panel according to claim 13, further comprising a non-display region located at least on one side of the display region; wherein in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line via a first data connecting line; the second intra-group data signal line is electrically connected to the fourth intra-group data signal line via a second data connecting line; the first data connecting line and the second data connecting line are both located in the non-display region; the second data connecting line is located on a side of the first data connecting line close to the display region, and the second data connecting line and the third intra-group data signal line are located in different layers; or the first data connecting line is located on a side of the second data connecting line close to the display region, and the first data connecting line and the second group of data signal lines are located in different layers.
The display panel according to claim 3, wherein in the first pixel circuit column group, the first intra-group data signal line is electrically connected to the third intra-group data signal line via a first data connecting line; the second intra-group data signal line is electrically connected to the fourth intra-group data signal line via a second data connecting line; the first data connecting line and the second data connecting line are located in a same layer, or the first data connecting line and the second data connecting line are located in different layers.
The display panel according to claim 2, wherein the third data signal line comprises a first sub-data signal line and a second sub-data signal line; in the row direction, the first sub-data signal line and the second sub-data signal line are located on different sides of the second pixel circuit column.
The display panel according to claim 2, wherein the third data signal line comprises a first sub-data signal line and a second sub-data signal line; the first sub-data signal line is electrically connected to the third pixel circuits of odd-numbered rows in the second pixel circuit column; and the second sub data signal line is electrically connected to the third pixel circuits of even-numbered rows in the second pixel circuit column.
The display panel according to claim 2, wherein the third data signal line comprises a first sub-data signal line and a second sub-data signal line; the first sub-data signal line is electrically connected to all of the third pixel circuits in the second pixel circuit column; and the second sub data signal line is electrically connected to all of the third pixel circuits in the second pixel circuit column.
The display panel according to claim 17 or 18, wherein the first sub-data signal line and the second sub-data signal line connected to a same second pixel circuit column are electrically connected to each other.
The display panel according to claim 19, further comprising a non-display region located at least on one side of the display region; wherein the first sub-data signal line and the second sub-data signal line connected to the same second pixel circuit column are electrically connected to each other via a third data connecting line; the third data connecting line is located in the non-display region.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to Chinese Patent Application No. 202411259179.2 filed on September 9, 2024, and titled "DISPLAY PANEL AND DISPLAY DEVICE", which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the technical field of display technology, and in particular to a display panel and a display device. BACKGROUND In order to improve the display effect of the display panel, in the related art, there is a situation where sub-pixels of different colors receive data signals transmitted via a same data signal line. In such configuration, the power consumption of the display panel is increased. SUMMARY The present disclosure provides a display panel and a display device, so as to reduce the power consumption of the display panel while ensuring the display effect. According to an aspect of the present disclosure, a display panel is provided, comprising a display region, the display region comprises a plurality of pixel circuits arranged in an array, the plurality of pixel circuits comprising a first pixel circuit, a second pixel circuit and a third pixel circuit. The first pixel circuit, the second pixel circuit and the third pixel circuit are respectively connected to light-emitting elements of different colors. The display panel further comprises a plurality of data signal lines, the plurality of data signal lines comprises a first data signal line, a second data signal line and a third data signal line. The first data signal line is electrically connected to the first pixel circuit, the second data signal line is electrically connected to the second pixel circuit, and the third data signal line is electrically connected to the third pixel circuit. According to another aspect of the present disclosure, a display device is provided, comprising the display panel according to the first aspect. In the display panel and the display device provided by embodiments of the present disclosure, one data signal line is connected only to sub-pixels emitting light of a same color, so that one data signal line only need to transmit a data signal corresponding to the sub-pixels of one color, thereby reducing the switch frequency and switch amplitude of the data signal on a single data signal line, and reducing the power consumption of the integrated circuit (IC) providing the data signal, which is beneficial to reducing the overall power consumption of the display panel. It should be understood that the contents described here are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. Fig. 1 is a schematic structural diagram of a display panel in the related art;Fig. 2 is a timing diagram of a data signal on a data signal line in the display panel shown in Fig. 1;Fig. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;Fig. 4 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;Fig. 5 is a cross-sectional diagram of a sub-pixel provided by an embodiment of the present disclosure;Fig. 6 is a timing diagram of a data signal on a data signal line provided by an embodiment of the present disclosure;Fig. 7 is a schematic structural diagram of a display panel provided by another embodiment of the present disclosure;Fig. 8 is a schematic structural diagram of a display panel provided by yet another embodiment of the present disclosure;Fig. 9 is a schematic structural diagram of a display panel provided by yet another embodiment of the present disclosure;Fig. 10 is a partial cross-sectional diagram of a display panel provided in an embodiment of the present disclosure;Fig. 11 is a schematic structural diagram of a display panel provided by another embodiment of the present disclosure;Fig. 12 is a schematic structural diagram of a display panel provided by yet another embodiment of the present disclosure;Fig. 13 is a partial cross-sectional diagram of a display panel provided by yet another embodiment of the present disclosure;Fig. 14 is a partial cross-sectional diagram of a display panel provided by yet another embodiment of the present disclosure;Fig. 15 is a schematic structural diagram of a display panel provided by yet another embodiment of the present disclosure;Fig.