FREQUENCY ADJUSTED SYNCHRONIZER FOR CLOCK DOMAIN CROSSING

Abstract

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113). These flip-flops receive input data (A_q) from a first clock domain (107) and output data (120) from the second clock domain (114). The second clock signal has a variable frequency, adjusted to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are thus avoided. Figure for the summary: Figure 3

Inventors

Jérôme Lacan
Christophe Eva

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260508
Application Date: 20241104