Memory device with memory cell array

Abstract

Memory Device with Memory Cell Array Memory device (100) comprising a memory cell array (102.1-102.4), each cell containing M memory elements (106), and a switch (104), the memory cells being addressed by word lines (108), source lines (112), and bit lines (110), wherein: - a first conduction electrode of each switch is coupled to a first electrode of each of the memory elements in a single memory cell; - each word line is coupled to a control electrode of each switch in a single column of memory cells; - each source line is coupled to a second conduction electrode of each switch in a single row of memory cells; - each bit line is coupled to a second electrode of one of the memory elements in each memory cell in a single column of memory cells. Figure for the abstract: Fig. 1

Inventors

Thomas BAUVENT
Gaël Pillonnet
Gabriel Molas

Assignees

Commissariat à l'Energie Atomique et aux Energies Alternatives

Dates

Publication Date: 20260508
Application Date: 20241105