3-transistor footprint stacked SRAM

Abstract

There are processing methods and resulting structures for providing three-transistor (3T) footprint stacked SRAMs. An SRAM bit cell includes a first inverter positioned at a first obtuse corner of a parallelogram. The first inverter includes a first pull-up transistor (PU) vertically stacked over a first pull-down transistor (PD) . The SRAM bit cell includes a second inverter positioned at a second obtuse corner of the parallelogram. The second inverter includes a second PU vertically stacked over a second PD. A first pass-gate (PG) is positioned at a first acute corner of the parallelogram and a second PG is positioned at a second acute corner of the parallelogram.

Inventors

CHEN ZHANG
SHAY REBOH
RUILONG XIE
DEBARGHYA SARKAR

Assignees

IBM

Dates

Publication Date: 20260506
Application Date: 20250319
Priority Date: 20250319