JP-2022511949-A5 -

Dates

Publication Date

20221207

Application Date

20191220

Description

Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, and chalcogenide memory technology. Memory cells may be volatile or non-volatile. Generally, a single memory cell 105 may be located at the intersection of access lines 120 and 130 (for example, coupled to them and coupled between them). This intersection, or indication of this intersection, may be referred to as the address of the memory cell 105. The target or selected memory cell 105 may be a memory cell 105 located at the intersection of an energized or selected access line 120 and an energized or selected access line 130. In other words, access lines 120 and 130 may be energized or selected to access (read, write, overwrite (rewrite) , refresh) the memory cell 105 at their intersection. Other memory cells 105 that are electronically communicating with (for example, connected to) the same access line 120 or 130 may be referred to as untargeted or unselected memory cells 105. In the case of capacitive memory elements, the memory cell 105 may be written by applying a voltage to the capacitor, then isolating the capacitor (for example, by isolating the capacitor from the voltage source used to write to the memory cell 105, thereby floating the capacitor) and storing a charge associated with the desired logic state in the capacitor. In the case of ferroelectric (ferroelectric) memory, the ferroelectric memory element (e.g., ferroelectric capacitor) of the memory cell 105 may be written by applying a voltage large enough to polarize the ferroelectric memory element by polarization associated with the desired logic state (e.g., applying a saturation voltage), and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage or bias may be applied across the entire ferroelectric memory element (e.g., grounding, virtual grounding, or voltage equalization across the entire ferroelectric memory element). In the case of PCM, the memory element may be written by applying a current profile that causes the memory element to form an atomic configuration associated with the desired logic state (e.g., by heating and cooling). In some examples, a memory device can use the CAM to determine whether data associated with an received access command is stored in the signal -deployed cache. Accessing the signal-deployed cache of a memory device may be less time-consuming than accessing a larger memory array. In such examples, the duration used to perform the access operation may be reduced based on the identification using the CAM that the data is stored in the signal -deployed cache. In response to an access command, the system may refer to one or more mappings stored in the CAM to determine whether to access information stored in the signal-deployed cache or information stored in the memory array. In one example, a memory controller may receive a read command from a requesting device (e.g., a control device ) from a first address in the memory array. The memory controller can use the mapping information from the CAM to determine that information stored at the first address in the memory array is also stored in the signal -deployed component array. Based on this determination, the memory controller may access the signal-deployed component array to retrieve (obtain) the information associated with the read command. The digit line 210 may have properties that result in a true capacitance (intrinsic capacitance) 230 (e.g., equivalent to a picofarad (pF), which may in some cases be non-negligible), thereby allowing the digit line 210 to be coupled to a voltage source 240-a having a voltage V0. The voltage source 240-a may represent a common ground voltage or a virtual ground voltage, or the voltage of an adjacent access line of the circuit 200 (not shown). Although shown as a separate element in Figure 2, the true capacitance 230 may be associated with properties distributed throughout the digit line 210 or another entire portion of the circuit 200. In some examples, the duration or latency for deploying a cell access signal may be expressed as a time constant (e.g., the time to reach 63% of the change between the initial voltage and the steady-state voltage), or as a multiple of the time constant. For example, the duration or latency for deploying a cell access signal may be expressed as a duration of three times the time constant, or as the duration associated with the cell access signal that is within 5% of the steady-state value. In another example, the duration or latency for deploying a cell access signal may be expressed as a duration of five times the time constant, or as the duration associated with the cell access signal that is within 1% of the steady-state value. In some e