JP-2022539328-A5 -

Dates

Publication Date

20230518

Application Date

20200601

Description

[0064] The foregoing disclosures are illustrative examples of the present disclosure, but it should be noted that various changes and modifications can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and/or operations of the method claims in the examples of the disclosure described herein do not need to be performed in any particular order. Furthermore, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the embodiments and examples disclosed herein. Furthermore, elements of the present disclosure may be described or claimed in the singular, but unless a limitation to the singular is expressly stated, the plural is intended. The invention described in the original claims of this application is listed below. [C1] Bit cell circuit, A bit cell coupled to the system voltage and ground, A first signal line connected to the bit cell, A second signal line connected to the bit cell, A third signal line connected to the bit cell, A fourth signal line connected to the bit cell, A first read signal line, the output of the bit cell, and a read transistor coupled to the first read bit line, A capacitor coupled to the bit cell output and the system voltage A bit cell circuit equipped with the following features. [C2] The bit cell circuit according to [C1], wherein the bit cell comprises a first transistor coupled to the first signal line, a second transistor coupled to the second signal line, a third transistor coupled to the third signal line, and a fourth transistor coupled to the fourth signal line. [C3] The bit cell circuit described in [C2], wherein the bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latching function with respect to the data bit. [C4] The bit cell circuit described in [C2], wherein the first transistor is a P-type transistor, the second transistor is a P-type transistor, the third transistor is an N-type transistor, and the fourth transistor is an N-type transistor. [C5] The bit cell circuit described in [C1], wherein the reading transistor is an N-type transistor. [C6] The bit cell circuit according to [C1], wherein the bit cell circuit is configured to perform an XNOR operation on the first signal line, the second signal line, the third signal line, and the fourth signal line. [C7] The bit cell circuit is a charge-sharing static random access memory in computations in the memory array of a neural network, as described in [C1]. [C8] The capacitor provides a path to ground to prevent the output from floating, in the bit cell circuit described in [C1]. [C9] The bit cell circuit described in [C1] is incorporated into a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in automated vehicles. [C10] Bit cell circuit, A bit cell coupled to the system voltage and ground, A first signal line connected to the bit cell, A second signal line connected to the bit cell, A third signal line connected to the bit cell, A fourth signal line connected to the bit cell, A read transistor coupled to a first read signal line, the output of the bit cell, and the ground, A capacitor coupled to the bit cell output and the read bit line A bit cell circuit equipped with the following features. [C11] The bit cell circuit according to [C10], wherein the bit cell comprises a first transistor coupled to the first signal line, a second transistor coupled to the second signal line, a third transistor coupled to the third signal line, and a fourth transistor coupled to the fourth signal line. [C12] The bit cell circuit according to [C11], wherein the bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latching function on data bits. [C13] The bit cell circuit described in [C11], wherein the first transistor is a P-type transistor, the second transistor is a P-type transistor, the third transistor is an N-type transistor, and the fourth transistor is an N-type transistor. [C14] The bit cell circuit described in [C10], wherein the reading transistor is an N-type transistor. [C15] The bit cell circuit according to [C10], wherein the bit cell circuit is configured to perform an XNOR operation on the first signal line, the second signal line, the third signal line, and the fourth signal line. [C16] The bit cell circuit is a charge-sharing static random access memory in computations in the memory array of a neural network, as described in [C10]. [C17] The bit cell circuit described in [C10], wherein the capacitor provides a path to ground to prevent the output from floating. [C18] The bit cell circuit described in [C10] is incorpora