JP-2023164378-A5 -

Dates

Publication Date

20260508

Application Date

20230427

Description

The semiconductor stack layer 14 has a groove 16, which is used to expose the first semiconductor layer 11 to the outside of the active layer 12 and the second semiconductor layer 13. As shown in Figure 2B, in some embodiments, the groove 16 penetrates the active layer 12 and the second semiconductor layer 13. The protective layer 15 covers the upper surface of the second semiconductor layer 13, the sidewall of the first semiconductor layer 11, the sidewall of the active layer 12, the sidewall of the second semiconductor layer 13, and the upper surface of the first semiconductor layer 11 located within the groove 16. The protective layer 15 may be in direct contact with the substrate 10. In another embodiment, the protective layer 15 is not in contact with the substrate 10. The protective layer 15 has a first opening 5a within the groove 16 to expose a portion of the first semiconductor stack layer 11. The protective layer 15 has a second opening 5b in the second semiconductor layer 13 to expose a portion of the second semiconductor layer 13. The first electrode 3a is located within the groove 16 and has a portion formed on the protective layer 15, which covers the protective layer 15 located within the groove 16 and the portion of the protective layer 15 located outside the groove 16. The first electrode 3a has a first recess 6a formed within the first opening 5a and electrically connected to the first semiconductor layer 11. The first electrode 3a has a stepped outer shape where it is located in the groove 16. The second electrode 3b has a portion located on the protective layer 15 other than the second opening 5b, and a second recess 6b formed within the second opening 5b and electrically connected to the second semiconductor layer 13. Figures 2D to 2E show a semiconductor element 1' in another embodiment of the present disclosure. Its structure can be described in Figures 2A to 2B and the related paragraphs. As shown in Figure 2D, the conductive bumps 2a and 2b have outwardly projecting arc shapes and have vertices 21a and 21b. The vertices 21a and 21b are not at the same height. The vertices 21a are slightly lower than the vertices 21b. Figure 2E is a cross-sectional view of the semiconductor element 1' in Figure 2D along the BB' line segment. The conductive bump 2a is located above the groove 16, and when the volume of conductive bump 2a is close to that of conductive bump 2b, some of the conductive bump 2a needs to fill the groove 16, so the vertices 21a of conductive bump 2a are slightly lower than the vertices 21b of conductive bump 2b. In one embodiment, the first thickness H1 of the first conductive bump 2a is 0.4 to 1 μm smaller than the first thickness H1 of the first conductive bump 2a. 1, 1', 20 Semiconductor devices 2, 2a, 2b Conductive bumps 3, 3a, 3b electrode 4 Adhesive structure 5a First hole 5b Second hole 6a First recess 6b Second recess 7, 8 particles 10 circuit boards 11 First Semiconductor Layer 12 Active layer 13 Second Semiconductor Layer 14 Semiconductor Stack Layers 15 Protective layer 16 grooves 17 Lower surface 18 areas 19 Outermost edge 21, 21a, 21b top 22, 22a, 22b outermost surface 23a First bonding pad 23b Second bonding pad 24a, 24b top surface 30 Carriers (mounting units) 31 Mounting plate 32 Adhesive layer 33 areas 34 Indentations 40 Pickup Tools 41 Pickup section 50, 51 Target substrate 52 Conductive connection pads 53 Bonding layer 80, 84 Adhesive 81, 83 Resin 82 Conductive particles 151 Top surface 521 Side surface 1000, 1001, 1001', 2000 Semiconductor element array θ1, θ2 Enclosing angle D distance H1, H2, H3, H4, H5 Thickness L1, L2, L3 laser energy W1, W2, W3, W4 width