JP-2025515539-A5 -

Dates

Publication Date

20260507

Application Date

20230427

Description

Figure 7B is a schematic diagram of another data connection line arrangement according to an exemplary embodiment of the present disclosure, and is an enlarged view of area C1 in Figure 7A, showing the structure of 16 data signal lines, 4 data connection lines and 16 lead lines. As shown in Figure 7B , the first data signal line group includes four odd-numbered data signal lines (first data signal line 60-1, third data signal line 60-3, fifth data signal line 60-5 and seventh data signal line 60-7), the second data signal line group includes the remaining 12 data signal lines, and the first data signal lines 60-1 to the 16th data signal lines 60-16 can be installed sequentially along the first direction X. In an exemplary embodiment, the first group of leader lines includes four odd-numbered leader lines (first leader line 80-1, third leader line 80-3, fifth leader line 80-5, and seventh leader line 80-7), the second group of leader lines includes the remaining twelve leader lines, the multiple leader lines of the first group of leader lines may be installed sequentially along the opposite direction of the first direction X, the multiple leader lines of the second group of leader lines may be installed sequentially along the first direction X, and two leader lines of the second group of leader lines are installed between adjacent leader lines of the first group of leader lines. For example, the multiple leader lines may include the second leader line 80-2, the fourth leader line 80-4, the sixth leader line 80-6, the eighth leader line 80-8, the ninth leader line 80-9, the seventh leader line 80-7, the tenth leader line 80-10, the eleventh leader line 80-11, the fifth leader line 80-5, the twelfth leader line 80-12 , the thirteenth leader line 80-13, the third leader line 80-3, the fourteenth leader line 80-14 , the fifteenth leader line 80-15, the first leader line 80-1, and the sixteenth leader line 80-16, which are installed sequentially along the first direction X. In exemplary embodiments, the power supply wiring 90 may continuously supply low-level signals . For example, the power supply wiring 90 may be a second power supply line VSS. During the data writing period when refreshing the frame, the signals from the first scan signal line S1 and the third scan signal line S3 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. During this period, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 turns on, and the second transistor T2 and the fourth transistor T4 turn on, and as a result the data voltage output from the data signal line D is supplied to the second terminal of the storage capacitor C via the turned-on third transistor T3 and the turned-on second transistor T2. The turn-on of the seventh transistor T7 supplies the second initial voltage of the second initial signal line INIT2 to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing the voltage stored inside it, and completing the initialization. The signals from the second scan signal line S2 and the light emission signal line E turn off the first transistor T1, the fifth transistor T5, and the sixth transistor T6.