JP-2026074668-A - Error correction method and error correction circuit

Abstract

[Problem] To provide an error correction method and error correction circuit for a digital coherent optical transmission system that suppress increases in circuit size and power consumption even when the code length is large. [Solution] The error correction method of the present invention is a method that performs error correction multiple times, and in some error corrections, only the latter half of the code is targeted for correction. For the bits in the latter half of the code, error correction is performed using the LLR (log-likelihood ratio) input from the preceding circuit, and for the bits in the first half of the code, error correction is performed using the fixed maximum value that the LLR can take. [Selection Diagram] Figure 4

Inventors

• 滝之入（阿部） 淳子
• 遠藤 靖行

Assignees

• ＮＴＴイノベーティブデバイス株式会社

Dates

Publication Date

20260507

Application Date

20241021

Claims (9)

1. An error correction method for a digital coherent optical transmission system, characterized by performing multiple error corrections, and in some error corrections, only the latter half of the code being corrected.
2. In the error correction method described in claim 1, The first step is to calculate the bitwise LLR of the code to be error corrected, The process includes a second step of performing error correction using the aforementioned LLR, updating the LLR based on the error correction determination result, and outputting it to the subsequent circuit. An error correction method characterized in that, in a part of the second step which is performed multiple times, the latter half of the code bits are corrected using the LLR input from the preceding circuit, and the first half of the code bits are corrected using a fixed maximum value that the LLR can take.
3. In the error correction method described in claim 2, After processing in the first step, the processing in the second step is performed multiple times. The second step is characterized by including the step of performing error correction using the LLR input from the preceding circuit only for the latter half of the bits if the desired error correction performance can be obtained, and performing error correction on the first half of the bits using the fixed maximum value that the LLR can take, and performing error correction using the LLR input from the preceding circuit for all bits if the desired error correction performance cannot be obtained.
4. An error correction circuit for a digital coherent optical transmission system, characterized by performing multiple error corrections, and in some error corrections, only the latter half of the code being corrected.
5. In the error correction circuit according to claim 4, An error correction circuit further comprising a soft decision circuit that calculates the LLR for each bit of the code from the coordinate shift of the received symbol and outputs it to a subsequent circuit.
6. In the error correction circuit described in claim 5, The system includes multiple soft-decision decoding circuits that perform error correction processing using the aforementioned LLR and update the LLR based on the results. The soft-decision decoding circuit is characterized in that, when the desired error correction performance can be obtained, it performs error correction on only the latter half of a codeword consisting of multiple bits using the LLR input from the preceding circuit, and performs error correction on the first half of the codeword using the fixed highest value that the LLR can take, and when the desired error correction performance cannot be obtained, it performs error correction on all bits using the LLR output from the preceding circuit.
7. In the error correction circuit according to claim 6, An error correction circuit characterized in that, among the multiple stages of the soft-decision decoding circuit, error correction is performed only in the final stage soft-decision decoding circuit, with the LLR of the first half bits set to the maximum value, while in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit.
8. In the error correction circuit according to claim 6, An error correction circuit characterized in that, in all of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, and error correction of the second half bits is performed using the LLR output from the preceding circuit.
9. In the error correction circuit according to claim 6, An error correction circuit characterized in that, in some of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, and error correction of the second half bits is performed using the LLR output from the preceding circuit, and in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit.

Description

This invention relates to an error correction method and error correction circuit for a digital coherent optical transmission system. Error correction is a technique that corrects bit errors occurring in the transmission path by adding error correction codes (parity bits) to the transmitted code (information bits) at the transmitting end, and then using the received error correction codes (parity bits) at the receiving end to correct errors in the received code (information bits). To further increase the capacity and speed of optical communication, long-distance transmission of signals exceeding 100 Gbps is required, and the use of digital coherent optical transmission methods is expected. In the transmission of signals exceeding 100 Gbps, the influence of transmission path noise becomes significant, requiring advanced error correction. In digital coherent optical transmission, high error correction capability is achieved not only through conventional hard judgment but also through soft judgment and repeated decoding (see Patent Document 1). When error correction processing is performed on the receiving end, the LLR (Log-Likelihood Ratio) is used as soft-decision information, which is the input to the error correction decoding circuit. This LLR is derived from the coordinate shift of the received symbol and is calculated from the ratio of the probability that the transmitted signal is 0 to the probability that it is 1. The absolute value of the LLR indicates the likelihood of the 1/0 judgment result for the received code. Conventional error correction technologies require the retention of LLR (Long Life Count) for the entire code length during the error correction process. This leads to increased circuit size and power consumption in error correction processes involving large code lengths. Patent No. 7241851 Figure 1 is a block diagram showing the configuration of the transmitting device of a digital coherent optical transmission system according to an embodiment of the present invention.Figure 2 is a block diagram showing the configuration of a receiving device in a digital coherent optical transmission system according to an embodiment of the present invention.Figure 3 is a block diagram showing the configuration of a soft judgment circuit and an error correction decoding circuit according to an embodiment of the present invention.Figure 4 is a flowchart illustrating the operation of the soft judgment circuit and error correction decoding circuit according to an embodiment of the present invention.Figure 5 illustrates the overall arrangement of codes and the placement of each code in oFEC.Figure 6 illustrates the sign overlap in oFEC.Figure 7 illustrates the overlap of symbols in oFEC. The following describes embodiments of the present invention with reference to the drawings. Figure 1 is a block diagram showing the configuration of the transmitting device of a digital coherent optical transmission system according to an embodiment of the present invention. Figure 2 is a block diagram showing the configuration of the receiving device of a digital coherent optical transmission system according to an embodiment of the present invention. The transmitting device 1 generates a transmission signal by encoding and modulating the transmission data. The transmission signal is received by the receiving device via a wired or wireless transmission path. The receiving device demodulates and decodes the received signal to generate received data. The transmitting device 1 includes an error correction coding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a D/A conversion circuit 13. The error correction coding circuit 10 generates coded data by performing, for example, BCH (Bose-Chaudhuri-Hocquenghem) coding or LDPC (Low Density Parity Check) coding on the transmitted data. The symbol mapping circuit 11 performs carrier modulation by assigning the encoded data output from the error correction coding circuit 10 to symbol points such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation). The modulation circuit 12 generates a modulated signal by applying, for example, OFDM (Orthogonal Frequency Division Multiplexing) modulation to the data carrier-modulated by the symbol mapping circuit 11. The DA conversion circuit 13 converts the modulated signal from a digital signal to an analog signal to generate a transmission signal. The transmission signal is converted to an optical signal by an optical transmission module (not shown) and sent to the optical fiber transmission path. The receiving device 2 includes an A/D conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, a soft decision circuit 23, and an error correction decoding circuit 24. The optical receiving module (not shown) of the receiving device 2 converts the optical signal received from the optical fiber transmission line into an analog received signal. The AD conversion circuit 20 conver