Search

JP-2026075024-A - High-frequency component testing apparatus and method thereof

JP2026075024AJP 2026075024 AJP2026075024 AJP 2026075024AJP-2026075024-A

Abstract

[Problem] To provide a high-frequency component testing apparatus and method that can reduce calibration errors. [Solution] A high-frequency component test apparatus 100 is provided, which includes a test key and a test module. The test key 105 includes a pre-key 110 and a post-key 120 that are symmetrically arranged and have the same electrical length and characteristic impedance. The test module 130 is used to measure the S-parameters of the directly connected pre-key and post-key, and the S-parameters of a structure in which the device under test (DUT) is added between the pre-key and post-key. The test module performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses matrix root open operations and inverse matrix operations to determine the ABCD parameters of the unembedded DUT. [Selection Diagram] Figure 5

Inventors

  • 李思翰
  • 張傑
  • 梅▲ペン▼翌

Assignees

  • 財團法人工業技術研究院

Dates

Publication Date
20260507
Application Date
20241220
Priority Date
20241021

Claims (15)

  1. A first test key includes a first front-level key and a first back-level key, which are symmetrically arranged and have the same electrical length and characteristic impedance. The system comprises a test module used to measure the S-parameters of the directly connected first pre-key and first post-key, and the S-parameters of a structure under test in which a device under test (DUT) is added between the first pre-key and the first post-key, The aforementioned test module is a high-frequency component test apparatus that performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses matrix root open operations and inverse matrix operations to obtain the ABCD parameters of a non-embedded DUT.
  2. The second test key is further equipped, The test apparatus according to claim 1, wherein the second test key includes a directly connected second pre-key, a first line segment, and a second post-key, and the first line segment is electrically connected between the second pre-key and the second post-key.
  3. The third test key is further equipped, The test apparatus according to claim 2, wherein the third test key includes a directly connected third pre-key, a second line segment, and a third post-key, the second line segment is electrically connected between the third pre-key and the third post-key, and the length of the second line segment is twice the length of the first line segment.
  4. [PAD] is the ABCD parameter matrix of the first pre-key and the first post-key, [Dem1] is the ABCD parameter matrix when the first pre-key and the first post-key are directly connected, [Dem1] = [PAD] [PAD], The ABCD parameter matrices of the first pre-key and the first post-key are: The test apparatus according to claim 3, as expressed as follows.
  5. [PAD] is the ABCD parameter matrix of the second pre-key and the second post-key, [Line1] is the ABCD parameter matrix of the first line segment, [Dem2] is the ABCD parameter matrix when the second pre-key, the first line segment, and the second post-key are directly connected, The test apparatus according to claim 4, wherein [Dem2] = [PAD] [Line1] [PAD].
  6. [PAD] is the ABCD parameter matrix of the third pre-key and the third post-key, [Line2] is the ABCD parameter matrix of the second line segment, [Dem3] is the ABCD parameter matrix when the third pre-key, the second line segment, and the third post-key are directly connected. The test apparatus according to claim 5, wherein [Dem3] = [PAD] [Line2] [PAD].
  7. The test module verifies that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment. The ABCD parameter matrix of the second line segment in the third test key is: The test apparatus according to claim 6, wherein [Line2] = [Line1] [Line1].
  8. [Golden] is the ABCD parameter matrix of the non-embedded DUT, [DUT] is the ABCD parameter matrix when the first pre-key, the DUT, and the first post-key are directly connected. [DUT] = [PAD] [Golden] [PAD], The ABCD parameter matrix of the non-embedded DUT is calculated according to the inverse of the ABCD parameter matrix of the first pre-key and the first post-key. The test apparatus according to claim 7, wherein [Golden] = [PAD] - 1 [DUT] [PAD] - 1 .
  9. A step of supplying a first test key, a second test key, and a third test key, wherein the first test key includes a directly connected first pre-stage key and a first post-stage key, the pre-stage key and the post-stage key are arranged symmetrically and have the same electrical length and characteristic impedance; the second test key includes a directly connected second pre-stage key, a first line segment, and a second post-stage key, the first line segment is electrically connected between the second pre-stage key and the second post-stage key; the third test key includes a directly connected third pre-stage key, a second line segment, and a third post-stage key, the second line segment is electrically connected between the third pre-stage key and the third post-stage key, and the length of the second line segment is twice the length of the first line segment; A step of measuring the S-parameters of the directly connected first pre-key and first post-key, the S-parameters of the directly connected second pre-key, first line segment, and second post-key, the S-parameters of the directly connected third pre-key, second line segment, and third post-key, and the S-parameters of a structure in which a device under test (DUT) is added between the first pre-key and the first post-key, The process involves performing S-parameter calculations in the frequency domain, converting the S-parameters into an ABCD parameter matrix, and obtaining the ABCD parameter matrix of the first pre-key and the first post-key using a root open operation. A step of verifying that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment in the second test key, A step of calculating the ABCD parameters of the unembedded DUT according to the inverse matrix of the ABCD parameter matrices of the first pre-key and the first post-key, A high-frequency component testing method, including the following.
  10. The test method according to claim 9, wherein the first test key, the second test key, and the third test key have the same characteristic impedance.
  11. [PAD] is the ABCD parameter matrix of the first pre-key and the first post-key, [Dem1] is the ABCD parameter matrix when the first pre-key and the first post-key are directly connected, [Dem1] = [PAD] [PAD], The ABCD parameter matrix of the first pre-key and the first post-key is, The test method according to claim 9, expressed as follows.
  12. [PAD] is the ABCD parameter matrix of the second pre-key and the second post-key, [Line1] is the ABCD parameter matrix of the first line segment, [Dem2] is the ABCD parameter matrix when the second pre-key, the first line segment, and the second post-key are directly connected, The test method according to claim 11, wherein [Dem2] = [PAD] [Line1] [PAD].
  13. [PAD] is the ABCD parameter matrix of the third pre-key and the third post-key, [Line2] is the ABCD parameter matrix of the second line segment, [Dem3] is the ABCD parameter matrix when the third pre-key, the second line segment, and the third post-key are directly connected, The test method according to claim 12, wherein [Dem3] = [PAD] [Line2] [PAD].
  14. It was verified that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment. The ABCD parameter matrix of the second line segment in the third test key is: The test method according to claim 13, wherein [Line2] = [Line1] [Line1].
  15. [Golden] is the ABCD parameter matrix of the unembedded DUT, [DUT] is the ABCD parameter matrix when the first pre-key, the DUT, and the first post-key are directly connected. [DUT] = [PAD] [Golden] [PAD], The ABCD parameter matrix of the non-embedded DUT is calculated according to the inverse of the ABCD parameter matrix of the first pre-key and the first post-key. The test method according to claim 14, expressed as [Golden] = [PAD] - 1 [DUT] [PAD] - 1 .

Description

Detailed description of the invention (background) (Technical field) This disclosure relates in general to test equipment, and more particularly to high-frequency component test equipment and test methods thereof. (Explanation of related technologies) Traditionally, SOLT or TRL have been primarily used for measuring and calibrating high-frequency components. SOLT requires four calibration kits: short, open, through, and load. TRL requires three sets of test keys, including through, reflect, and line keys. The above calibration techniques typically involve complex calibration procedures because they use different calibration methods depending on the specific measurement requirements (such as broadband frequencies or on-wafer probing). Furthermore, in calibration methods using SOLT and TRL, errors occurring in each measurement easily affect the calibration results. For example, differences in probing depth or misalignment of the probing position will affect the calibration results. Therefore, providing solutions that can avoid inaccurate measurements of the device under test (DUT) caused by calibration errors is a crucial challenge for the industry. U.S. Patent Application Publication No. 20100315115 A1, titled "METHOD OF CHARACTERIZING A SEMICONDUCTOR DEVICE," discloses a method for characterizing a semiconductor device. This method provides a silicon-on-insulator (SOI) substrate having at least a body-tie (BT) SOI device and a BT dummy device for measurement. The method includes measuring the tunnel current (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, respectively. The Igb of the floating-body (FB) SOI device is obtained by subtracting the Igb of the BT dummy device from the Igb of the BT SOI device. The S-parameters of the FB SOI device are extracted by filtering the characteristics of the BT dummy device, and the gate-related capacitance of the FB SOI device is determined by analyzing the S-parameters of the FB SOI device. (overview) This disclosure is directed to a high-frequency component testing apparatus and method capable of reducing calibration errors. According to one embodiment of the present disclosure, a high-frequency component test apparatus is provided, comprising a first test key and a test module. The first test key includes a first pre-key and a first post-key, which are symmetrically arranged and have the same electrical length and characteristic impedance. The test module is used to measure the S-parameters of the directly connected pre-key and post-key, and the S-parameters of the structure under test with the device under test (DUT) added between the pre-key and post-key. The test module performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses matrix root-open and inverse operations to obtain the ABCD parameters of the unembedded DUT. According to another embodiment of this disclosure, a high-frequency component test method is provided. The high-frequency component test method includes the following steps: A test key is provided, including a pre-key and a post-key, where the pre-key and post-key are symmetrically arranged and have the same electrical length and characteristic impedance. The S-parameters of the directly connected pre-key and post-key are measured, as well as the S-parameters of a structure in which the device under test (DUT) is added between the pre-key and post-key. The S-parameter calculation is performed in the frequency domain, the S-parameters are converted into an ABCD parameter matrix, and the ABCD parameter matrix of the pre-key and post-key is obtained by root-open operation. The ABCD parameters of a non-embedded DUT are calculated according to the inverse of the ABCD parameter matrix of the pre-key and post-key. The above and other aspects of this disclosure will be better understood in relation to the following detailed description of preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. (Brief explanation of the drawing) Figures 1 and 2 are schematic diagrams of a high-frequency component testing apparatus according to one embodiment of the present disclosure. Figure 3 is a flowchart of a high-frequency component testing method according to one embodiment of the present disclosure. Figures 4A to 4D are schematic diagrams illustrating the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure. Figures 5 and 6 are schematic diagrams of a high-frequency component testing apparatus according to another embodiment of the present disclosure, respectively. Figures 7 and 8 are schematic diagrams of the second and third test keys used in a high-frequency component testing apparatus, respectively. Figure 9 shows a flowchart of a high-frequency component testing method according to one embodiment of the present disc