JP-2026075034-A - Integrated LDPC and RAID Decryption Method

Abstract

[Problem] To provide a data storage device that handles errors resulting from physical defects. [Solution] The error correction code (ECC) system of the data storage device utilizes an integrated decoding scheme to correct errors in a codeword when the decoding process using a first decoding scheme fails, and uses information derived from a second decoding scheme to generate soft bit information or reliability information associated with the failed portion of the codeword. The soft bit information derived from the second decoding scheme is provided to the first decoding scheme when the first decoding scheme attempts to correct or decode the failed codeword. [Selection Diagram] Figure 1

Inventors

• エラン シャロン
• アレクサンダー バザルスキー
• ラン ザミール

Assignees

• サンディスク テクノロジーズ インコーポレイテッド

Dates

Publication Date

20260507

Application Date

20250425

Priority Date

20241021

Claims (20)

1. It is a method, The codeword determines that the first decoding process using the first decoding scheme has failed, Identifying first parity information and second parity information associated with a portion of a codeword, at least in part on determining that the codeword failed in the first decoding process using the first decoding scheme, wherein the first parity information and the second parity information are associated with the second decoding scheme. Adjusting the reliability of the portion of the codeword based at least partially on the first parity information and the second parity information, A method comprising providing the reliability of the portion of the codeword to the first decoding scheme for a second decoding process.
2. The method according to claim 1, wherein the first decoding method is a low-density parity check (LDPC) decoding method.
3. The method according to claim 1, wherein the second decoding method is a redundant array (RAID) decoding method using independent dies.
4. The method according to claim 1, wherein the first parity information is at least partially based on an XOR operation performed on different portions of the striped codeword associated with the codeword.
5. The method according to claim 1, wherein the second parity information is at least partially based on multiplying a different portion of the striped codeword associated with the codeword by the codebook associated with the second decoding scheme.
6. The method according to claim 1, wherein the reliability of the portion of the codeword is adjusted when the first parity information matches the second parity information.
7. The method according to claim 6, further comprising increasing the reliability of the portion of the codeword based at least in part on a determination that the first parity information and the second parity information match the hard bit information associated with the codeword.
8. The method according to claim 6, further comprising reducing the reliability of the portion of the codeword based at least in part on a determination that the first parity information and the second parity information do not match the hard bit information associated with the codeword.
9. A data storage device, Controller and An error correction code (ECC) system associated with the controller, Identify codewords having a number of errors that exceeds the correction capability of the first decoding scheme, Identify the first parity information and the second parity information associated with the codeword, and the first parity information and the second parity information are associated with the second decoding scheme. A data storage device comprising: an error correction code (ECC) system capable of calculating the reliability of a portion of a codeword based at least partially on the first parity information and the second parity information, and providing the reliability of the portion of the codeword to a first decoding scheme.
10. The data storage device according to claim 9, wherein the first parity information is at least partially based on an XOR operation performed on different portions of the striped codeword associated with the codeword.
11. The data storage device according to claim 9, wherein the second parity information is at least partially based on multiplying a different portion of the striped codeword associated with the codeword by the codebook associated with the second decoding scheme.
12. The data storage device according to claim 9, wherein calculating the reliability of the portion of the codeword includes adjusting the reliability of the portion of the codeword if the first parity information matches the second parity information.
13. The data storage device according to claim 12, wherein calculating the reliability of the portion of the codeword further includes increasing the reliability of the portion of the codeword, at least in part, based on a determination that the first parity information and the second parity information match the hard bit information associated with the codeword.
14. The data storage device according to claim 12, wherein calculating the reliability of the portion of the codeword further comprises reducing the reliability of the portion of the codeword, at least in part, based on a determination that the first parity information and the second parity information do not match the hard bit information associated with the codeword.
15. A data storage device, Control means and Error correction means associated with the control means, Identifying multiple codewords having a number of errors that exceeds the correction capability of the first decoding method, It is determined that the number of the aforementioned codewords exceeds the correction capability of the second decoding method, Using the second decoding method described above, a list of potential codewords is generated using at least a portion of the stripe codewords associated with the first codeword among the plurality of codewords, A data storage device comprising error correction means operable to determine the reliability of each potential codeword in the list of codewords and to provide at least one potential codeword in the list of codewords to the first decoding scheme.
16. The data storage device according to claim 15, wherein the first decoding method is a low-density parity check (LDPC) decoding method, and the second decoding method is an independent die redundant array (RAID) decoding method.
17. The data storage device according to claim 15, wherein the list of potential codewords is ordered at least in part on the determined probability that each potential codeword in the list of potential codewords contains an error.
18. The data storage device according to claim 15, wherein the potential codewords in the list of potential codewords are ordered at least in part on the amount of error.
19. The data storage device according to claim 15, wherein the error correction means is further operable to compare at least a portion of the at least one potential codeword with reliability information associated with the first codeword.
20. The data storage device according to claim 15, wherein the error correction means is further operable to determine the combined reliability of each of the potential codewords in the list of potential codewords.

Description

Data storage devices typically include error correction capabilities to correct errors that occur when data is read from the data storage device. For example, when data is written to a data storage device, the data is encoded by an Error Correction Code (ECC) Low-Density Parity Check (LDPC) encoder to generate redundant information. This redundant information is known as parity bits. The parity bits and data are stored as an ECC codeword. When an ECC codeword is read from the data storage device, a decoder, such as an LDPC decoder, decodes the codeword and corrects any possible errors. Generally, LDPC decoders are used to correct random errors that occur on the data storage device. However, LDPC decoders cannot handle the large errors that result from memory defects and/or failures. Therefore, data storage devices can also incorporate redundant array (RAID) storage schemes of independent dies, designed to handle errors resulting from physical defects. For example, a RAID storage scheme distributes data along with first and second parity information in a stripe spanning multiple different solid-state drives (SSDs) or multiple different memory dies within a single SSD. The parity information allows for data recovery within the stripe in the event of failure of one of the SSDs or one of the memory dies. In some cases, LDPC decryption and RAID decryption are combined to increase the chances of error correction. For example, if multiple pages fail to decrypt, a RAID-based decryption method is implemented for those pages, followed by the LDPC decryption method. This process is repeated for each failed page. However, there may be situations where errors in the data exceed the correction capabilities of the LDPC and RAID decoders, but the bit error rate (BER) of the data is not high enough to indicate that the entire codeword is invalid or that the memory die has failed. Therefore, it would be beneficial to utilize RAID parity information in the LDPC decoding method in order to enable the LDPC decoding method to correct data with a high BER. This disclosure describes an error correction code (ECC) system for a data storage device. The ECC system utilizes an integrated decoding scheme to correct errors in a codeword (or flash memory unit) when at least one codeword or flash memory unit (FMU) fails the initial decoding process. For example, when a codeword fails the initial decoding process using a first decoding scheme (e.g., an LDPC decoding scheme), information derived from, or otherwise associated with, a second decoding scheme (e.g., a RAID decoding scheme) is used to generate soft bit information or reliability information associated with the failed portion of the codeword. The soft bit information derived from the second decoding scheme is provided to the first decoding scheme, which attempts to decode the previously failed codeword. Therefore, the information derived from, or associated with, the second decoding scheme can be used to correct random errors that cannot be corrected using the first decoding scheme, or when the number of memory defects is less (or more) than the correction capability of the second decoding scheme, but there are no memory defects. Therefore, an example of this disclosure describes a method that includes determining that a codeword has failed in a first decoding process using a first decoding scheme. Based at least in part on determining that the codeword failed in a first decoding process using a first decoding scheme, first and second parity information associated with the codeword portion is identified. In one example, the first and second parity information are associated with a second decoding scheme. The reliability of the codeword portion is adjusted at least in part on the first and second parity information. The reliability of the codeword portion is then provided to the first decoding scheme for the second decoding process. Another example describes a data storage device having a controller and an error correction code (ECC) system. In one example, the ECC system identifies codewords with a number of errors exceeding the correction capability of a first decoding scheme. The ECC system also identifies first and second parity information associated with the codewords. In one example, the first and second parity information are associated with a second decoding scheme. The ECC system calculates the reliability of a portion of the codeword. In one example, the reliability of a portion of the codeword is at least partially based on the first and second parity information. The ECC system also provides the reliability of a portion of the codeword to the first decoding scheme. Further examples describe a data storage device including control and error correction means. The error correction means is operable to identify a plurality of codewords having a number of errors exceeding the correction capability of a first decoding scheme. The error correction means is also operable to d