JP-2026075057-A - Semiconductor devices and methods for manufacturing the same

JP2026075057AJP 2026075057 AJP2026075057 AJP 2026075057AJP-2026075057-A

Abstract

[Problem] To provide a semiconductor device and a method for manufacturing the same that can form straighter channel materials. [Solution] The method for manufacturing a semiconductor device according to the present invention includes the following: S10 to provide a semiconductor structure including a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer. S20 to form a plurality of drain portions arranged in an array by damascene formation on the upper part of the second insulating layer. S30 to form a plurality of columnar structures arranged in an array on the upper surface of the source layer by etching the second insulating layer so that the plurality of drain portions are exposed to the source layer using the plurality of drain portions as a photomask. S40 to form a channel material layer surrounding the columnar structures along the circumferential direction. S50 to form a gate insulating layer and a gate structure on one side of the channel material layer away from the columnar structures. [Selection Diagram] Figure 1

Inventors

潘俊波

Assignees

深▲セン▼市昇維旭技術有限公司

Dates

Publication Date: 20260507
Application Date: 20250929
Priority Date: 20241021

Claims (13)

To provide a semiconductor structure including a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer, A plurality of drain portions are formed on the upper part of the second insulating layer, arranged in a damascene pattern, Multiple columnar structures are formed on the upper surface of the source layer by etching the second insulating layer so that the multiple drain portions are exposed on the source layer, wherein each columnar structure includes insulating posts located on the source layer and drain portions located on the insulating posts, and the multiple columnar structures are separated from each other by first trenches formed by etching the second insulating layer. Forming a channel material layer that surrounds the columnar structure along the circumferential direction, A gate insulating layer and a gate structure are formed on one side of the channel material layer that is separated from the columnar structure. A method for manufacturing semiconductor devices, including [the specified element].
Forming a plurality of drain portions arranged in an array on the upper part of the second insulating layer, which are formed as damascene, A first patterned resist layer is formed on the upper surface of the second insulating layer. Using the patterned resist layer as a photomask, the second insulating layer is etched to form a plurality of second trenches on the upper part of the second insulating layer that correspond one-to-one with the drain portions. Remove the patterned resist layer and fill the second trench with drain material. The drain portion is formed by polishing and removing the upper surface of the drain material by a chemical mechanical polishing process until it is co-surface with the upper surface of the second insulating layer. The manufacturing method according to claim 1, characterized by including
Forming the channel material layer surrounding the columnar structure along the circumferential direction includes depositing a semiconductor material layer on the inner wall surface of the first trench and on the upper surface of the columnar structure. The manufacturing method according to claim 1, characterized in that a portion of the semiconductor material layer surrounding the columnar structure along the circumferential direction constitutes the channel material layer.
The manufacturing method according to claim 3, further comprising performing a pre-cleaning treatment on the first trench and the columnar structure before forming the channel material layer that surrounds the columnar structure along the circumferential direction.
Performing a pre-cleaning treatment on the first trench and the columnar structure is When the drain portion is used as a photomask to etch the second insulating layer, the damaged upper surface of the drain portion is subjected to oxidation treatment. The oxide formed on the upper surface of the drain section is removed by a wet or dry method, and the first trench is cleaned. The manufacturing method according to claim 4, characterized by including
Forming the gate insulating layer and the gate structure on one side of the channel material layer that is separated from the columnar structure means that The gate insulating layer is formed so as to conformally cover the surface shape of the semiconductor material layer. A third insulating layer is formed by filling the first trench with insulating material and performing a surface planarization treatment, wherein the upper surface of the third insulating layer is higher than the upper surface of the gate insulating layer. A second patterned resist layer is formed on the upper surface of the third insulating layer. Using the second patterned resist layer as a photomask, the third insulating layer, the gate insulating layer, the semiconductor material layer, and the source layer are etched so as to be exposed from the first insulating layer, thereby forming a plurality of source line cut grooves, the source layer is stretched along a first direction and cut into a plurality of source lines arranged at intervals in a second direction, and each of the source lines is connected to a row of columnar structures arranged along the first direction, wherein both the first and second directions are parallel to the plane on which the first insulating layer exists, and the first and second directions intersect. A fourth insulating layer is formed by filling the source wire cut groove with insulating material and performing a surface planarization treatment, and the upper surface of the fourth insulating layer is higher than the gate insulating layer. By etching back the fourth insulating layer, a first etching back groove is formed, where the bottom of the first etching back groove is higher than the lowest upper surface of the gate insulating layer. To form the gate structure in the first etching back groove, The manufacturing method according to claim 3, characterized by including
Forming the gate structure within the first etching back groove means A gate material layer is formed by filling the first etching back groove with gate material and performing a surface planarization treatment. By etching back the gate material layer, a second etching back groove is formed, where the bottom of the second etching back groove is lower than the upper surface of the drain portion. A gate material is filled into the second etching back groove and a surface planarization treatment is performed to form a fifth insulating layer. A third patterned resist layer is formed on the upper surface of the fifth insulating layer. Using the third patterned resist layer as a photomask, the fifth insulating layer and the gate material layer are etched so as to be exposed from the gate insulating layer to form a plurality of word line cut grooves, the gate material layer is stretched along the second direction and cut into a plurality of word lines arranged at intervals in the first direction, each of the word lines connects to a row of columnar structures arranged along the second direction, where a portion of the word lines that curve around the side of the gate insulating layer away from the columnar structures constitute the gate structure. Fill the word line cut groove with insulating material and perform surface planarization treatment until it is exposed from the upper surface of the drain portion. The manufacturing method according to claim 6, characterized by including
The gate material layer includes a composite layer of a barrier layer and a gate metal layer. Filling the first etching back groove with gate material and performing a surface planarization treatment to form the gate material layer is, The barrier layer is conformally deposited on the inner surface of the first etching back groove and the uppermost surface of the gate insulating layer. The gate metal layer is formed by filling the remaining space of the first etching back groove with gate metal material and performing a surface planarization treatment, and the upper surface of the gate metal layer is higher than the uppermost upper surface of the barrier layer. Forming the second etching back groove by etching back against the gate material layer is, By etching back the barrier layer and the gate metal layer, the uppermost surface of the barrier layer and the upper surface of the gate metal layer become coplane, and are lower than the upper surface of the drain portion. The manufacturing method according to claim 7, characterized in that it
The aforementioned barrier layer is a titanium nitride layer, The gate metal layer is a tungsten layer. The manufacturing method according to claim 8.
The manufacturing method according to claim 6, characterized in that the gate insulating layer includes a silicon dioxide layer and a silicon nitride layer sequentially deposited on the semiconductor material layer in accordance with its shape.
The manufacturing method according to claim 10, characterized in that, in forming the first etching back groove by etching back into the fourth insulating layer, a non-plasma dry etching process is used to perform back etching on the fourth insulating layer.
The source layer includes a tungsten layer, a titanium nitride layer, and a polysilicon layer that are sequentially deposited on the first insulating layer. The material of the drain section is polysilicon. The manufacturing method according to claim 1, characterized in that the material of the channel material layer is polysilicon.
A semiconductor device characterized by being manufactured by the manufacturing method described in any one of claims 1 to 12.

Description

This invention relates to the semiconductor technology field, and more specifically, to semiconductor devices and methods for manufacturing the same. In the manufacturing of conventional semiconductor devices with a vertical transistor structure, typically, a source layer and a first oxide layer on the source layer are formed, followed by the formation of a gate layer and a second oxide layer on the gate layer above the first oxide layer. Then, channel holes are formed through the second oxide layer, the gate layer, and the first oxide layer, and finally, a channel material layer is formed within the channel holes. The following drawings of the present invention are incorporated as part of the present invention and are intended to facilitate understanding of this application. The drawings illustrate embodiments and descriptions of the present invention and interpret the apparatus and principles of the present invention. In the drawings, they are as follows: This is a schematic diagram showing a general flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic cross-sectional view along the line X-X. Figure 3 is a schematic cross-sectional view along the line X-X. Figure 4 is a schematic cross-sectional view along the line X-X. Figure 5 is a schematic cross-sectional view along the line X-X. Figure 6 is a schematic cross-sectional view along the line X-X. Figure 7 is a schematic cross-sectional view along the line X-X. Figure 8 is a schematic cross-sectional view along the line X-X. Figure 9 is a schematic cross-sectional view along the line X-X. Figure 10 is a schematic cross-sectional view along the line X-X. Figure 11 is a schematic cross-sectional view along the line X-X. Figure 12 is a schematic cross-sectional view along the line X-X. Figure 13 is a schematic cross-sectional view along the line X-X. Figure 14 is a schematic cross-sectional view along the Y-Y line. Figure 15 is a schematic cross-sectional view along the Y-Y line. Figure 16 is a schematic cross-sectional view along the line X-X. Figure 16 is a schematic cross-sectional view along the Y-Y line. The following description includes numerous specific details to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention can be carried out without one or more of these details. In other examples, some technical features known in the art are omitted to avoid confusion with the pr