JP-2026075078-A - Hybrid oxide semiconductor/polysilicon transistors for high-density 2T0C gain cell eDRAM

Abstract

[Problem] To provide a device having a 2-transistor, 0-capacitor gain cell implementation, and a method for manufacturing the same. [Solution] The provided device includes a back-end obline-fitted two-transistor zero-capacitor gain cell, the two-transistor zero-capacitor gain cell including a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. [Selection Diagram] Figure 1

Inventors

• ムハンメド・アホサン・ウル・カリム
• ハルソノ・シムカ
• シュエリアン・ジュ
• アラヴィンド・クマール

Assignees

• サムスン エレクトロニクス カンパニー リミテッド

Dates

Publication Date

20260507

Application Date

20251020

Priority Date

20250912

Claims (20)

1. A two-transistor zero-capacitor gain cell in a backend obline structure, comprising a write transistor and a read transistor electrically connected to the write transistor, It has, The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. device.
2. The device according to claim 1, wherein the oxide semiconductor channel is stacked on the polysilicon channel.
3. The device according to claim 1, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on the first tier.
4. The device according to claim 1, wherein the write transistor overlaps with the read transistor.
5. The read transistor is connected to the write transistor by vias. The aforementioned two-transistor, zero-capacitor gain cell stores data using the parasitic capacitance of the vias. The device according to claim 1.
6. The read transistor has a gate, source, and drain, and the write transistor has a gate, source, and drain. The gate of the read transistor is electrically connected to the drain of the write transistor. The device according to claim 1.
7. The device according to claim 1, wherein the gate line of the read transistor is connected to the drain region of the write transistor via a via.
8. The device according to claim 1, wherein a portion of the gate line of the read transistor overlaps with a portion of the drain region of the write transistor, and a via connects the portion of the gate line of the read transistor to the portion of the drain region of the write transistor.
9. The read transistor has a gate, source, and drain, and the write transistor has a gate, source, and drain. The gate of the read transistor is electrically connected to the drain of the write transistor. The gate of the write transistor is electrically connected to the write word line, the source of the write transistor is electrically connected to the write bit line, the source of the read transistor is electrically connected to the read word line, and the drain of the read transistor is electrically connected to the read bit line. The device according to claim 1.
10. The gate of the read transistor is electrically connected to the drain of the write transistor. The aforementioned two-transistor zero-capacitor gain cell stores data using the parasitic capacitance of the gate of the read transistor. The device according to claim 1.
11. The device according to claim 1, wherein the read transistor is contained in a first chiplet, the write transistor is contained in a second chiplet, and the first chiplet is hybrid-bonded to the second chiplet.
12. The device according to claim 1, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.
13. A front-end obline structure with a logic chip, The aforementioned front-end obline structure is a back-end obline structure, and the back-end obline structure includes a layer, It has, The aforementioned layer has a two-transistor zero-capacitor gain cell including a read transistor and a write transistor electrically connected to the read transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. system.
14. The system according to claim 13, wherein the logic chip is electrically connected to the write transistor and the read transistor.
15. The system according to claim 13, wherein the oxide semiconductor channel is stacked on the polysilicon channel.
16. The system according to claim 13, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on top of the first tier.
17. The read transistor is connected to the write transistor by vias. The aforementioned two-transistor, zero-capacitor gain cell stores data using the parasitic capacitance of the vias. The system according to claim 13.
18. A first structure is manufactured using a front-end-of-line process, and the first structure includes a logic chip. The first tier is manufactured using a back-end obline process, and the first tier has a readout transistor for a 2-transistor 0-capacitor gain cell. A second tier is manufactured on the first tier using the backend obline process, and the second tier has a writing transistor for the two transistors and zero capacitor gain cell. A method having the following characteristics.
19. The method according to claim 18, wherein the first tier is manufactured on the first structure.
20. The method according to claim 18, wherein the first tier is joined to the first structure by hybrid bonding.

Description

(Cross-reference of related applications) This application claims priority based on U.S. Provisional Application No. 63/709,875, filed with the U.S. Patent and Trademark Office on 21 October 2024, the disclosures thereof incorporated herein by reference in their entirety. The dominance of artificial intelligence (AI) in modern society has enabled a wide range of transformative and new applications, from natural language processing to cancer diagnosis. Today's AI algorithms are highly memory-constrained. However, limited main memory capacity and bandwidth are bottlenecks, and data transfer from DRAM is costly. There is a need for high-speed, high-density, and energy-efficient memory to help alleviate the current energy-intensive architectures used in AI accelerators. High-density, high-capacity on-chip memory can reduce main memory capacity and bandwidth bottlenecks. One embodiment provides a highly reliable, back-end-of-line (BEOL) compliant two-transistor zero-capacitor (2T0C) gain cell implementation for high-density embedded dynamic random access memory (eDRAM). According to one aspect of one or more embodiments, a device is provided having a two-transistor-0-capacitor gain cell in a back-end obline structure, wherein the two-transistor-0-capacitor gain cell includes a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. According to another aspect of one or more embodiments, a system is provided comprising a front-end obline structure having a logic chip, and a back-end obline structure on the front-end obline structure, the back-end obline structure including a layer. The layer has a two-transistor zero-capacitor gain cell including a read transistor and a write transistor electrically connected to the read transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. According to one or more embodiments, a method is provided, comprising: manufacturing a first structure using a front-end obline process, the first structure comprising a logic chip; manufacturing a first tier using a back-end obline process, the first tier having a read transistor for a 2-transistor 0-capacitor gain cell; and manufacturing a second tier on the first tier using a back-end obline process, the second tier having a write transistor for the 2-transistor 0-capacitor gain cell. The above and/or other embodiments will become clearer and more readily apparent from the following description of various embodiments, which is made in connection with the attached drawings, including the following figures. This shows a 2-transistor 0-capacitor (2T0C) gain cell according to one embodiment. An example of a semiconductor memory device according to some embodiments is shown. Figures 3 and 4 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. Figures 3 and 4 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. Figure 1 shows a plan view of an exemplary composite layout of the 2T0C gain cell according to one of the embodiments. This shows a cross-sectional view taken along line A-A' in Figure 5, according to one of the embodiments. This shows a cross-sectional view taken along line B-B' in Figure 5, according to one of the embodiments. This shows a cross-sectional view taken along line C-C' in Figure 5, according to one of the embodiments. This shows a cross-sectional view taken along line D-D' in Figure 5, according to one of the embodiments. Figures 10 and 11 show plan views of tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. Figures 10 and 11 show plan views of tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. Figures 12 and 13 show cross-sectional views of an example of an embedded dynamic random access memory (eDRAM) according to some embodiments. Figures 12 and 13 show cross-sectional views of an example of an embedded dynamic random access memory (eDRAM) according to some embodiments. This shows a cross-sectional view of an example of a semiconductor memory device according to some embodiments. This shows a monolithic integrated three-dimensional (3D) eDRAM according to one of the embodiments. This shows a 3D eDRAM with heterogeneous integration according to some embodiments. A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some embodiments. A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some embodiments. When used in this specification, the phrase “at least one of A, B, or C” includes, within its scope, “A only,” “B only,” “C only,” “A and B,” “B and C,” “A a