JP-2026075098-A - Semiconductor equipment

Abstract

[Problem] To provide a semiconductor device that uses a unipolar transistor and does not allow a steady current to flow, while still representing a high or low level. [Solution] The semiconductor device 10 includes transistors 11 to 14, capacitive elements C11 and C12, first and second wirings, first and second input terminals, and an output terminal. The gate of the fourth transistor 14 is electrically connected to the first input terminal SI_IN, one terminal of the capacitive element C11, and the gate of transistor 11. The gate of transistor 12 is electrically connected to the second input terminal SIB_IN. One source or drain of transistor 11 is electrically connected to the first wiring VSS_IN, and the other is electrically connected to the other terminal of the capacitive elements C11 and C12, one source or drain of transistor 13, and the output terminal SO_OUT. The other source or drain of transistor 12 and the other source or drain of transistor 13 are electrically connected to the second wiring VDD_IN. [Selection Diagram] Figure 1

Inventors

• 井上 広樹
• 上妻 宗広
• 青木 健
• 深井 修次
• 赤澤 史佳
• 原田 伸太郎
• 長尾 祥

Assignees

• 株式会社半導体エネルギー研究所

Dates

Publication Date

20260507

Application Date

20260127

Priority Date

20181220

Claims (1)

1. First to fourth transistors, First and second capacitance elements, First and second wiring, First and second input terminals, It has an output terminal, Either the source or drain of the fourth transistor is electrically connected to the first wiring, The source or drain of the fourth transistor is electrically connected to one of the source or drain of the second transistor, one terminal of the second capacitive element, and the gate of the third transistor. The source or drain of the second transistor, the other of which is electrically connected to the second wiring, The gate of the fourth transistor is electrically connected to the first input terminal, one terminal of the first capacitive element, and the gate of the first transistor. The gate of the second transistor is electrically connected to the second input terminal. Either the source or the drain of the first transistor is electrically connected to the first wiring, The source or drain of the first transistor is electrically connected to the other terminal of the first capacitance element, the other terminal of the second capacitance element, the source or drain of the third transistor, and the output terminal. A semiconductor device in which the source or drain of the third transistor, the other of which is electrically connected to the second wiring.

Description

One embodiment of the present invention relates to a logic circuit constructed using unipolar transistors. Furthermore, one embodiment of the present invention relates to a semiconductor device. In this specification, a semiconductor device is defined as: This refers to all devices that can function by utilizing semiconductor properties. For example, integrated circuits, chips containing integrated circuits, electronic components with chips housed in packages, and electronic devices equipped with integrated circuits are examples of semiconductor devices. Furthermore, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. CMOS (Complementary Metal Oxide Se) is a circuit (also called a digital circuit or logic circuit) that handles digital signals represented as high-level or low-level (sometimes expressed as High or Low, H or L, 1 or 0, etc.). Microcontroller circuits are widely used. In most cases, logic circuits are supplied with both high and low power supply potentials; high levels are represented using the high power supply potential, and low levels are represented using the low power supply potential. Furthermore, CMOS circuits are constructed using, for example, n-channel and p-channel transistors formed on a single-crystal silicon substrate. A CMOS circuit has a circuit configuration in which an n-channel transistor and a p-channel transistor are connected in series between a high power supply potential and a low power supply potential. When the n-channel transistor is conducting, the p-channel transistor is not conducting, and when the n-channel transistor is not conducting, the p-channel transistor is conducting. In other words, after a high level or low level is determined, no through-current flows from the high power supply potential to the low power supply potential (excluding transistor off-currents, etc.). In cases where it is not possible to manufacture both n-channel and p-channel transistors, or when it is desirable to reduce the transistor manufacturing process for cost reduction or other reasons, a logic circuit may be constructed using only one of either n-channel or p-channel transistors (also called a unipolar transistor or single-channel transistor). For example, Patent Documents 1 and 2 disclose examples of drive circuits for semiconductor devices and display devices configured using unipolar transistors. This circuit configuration involves connecting two unipolar transistors in series between a high power supply potential and a low power supply potential. A first signal and a second signal (the first signal with its logic inverted, either high or low) are input to the gates of the transistors, preventing through-current from flowing from the high power supply potential to the low power supply potential. This method, using a first signal and a second signal with its logic inverted, is sometimes called a dual-rail circuit. Furthermore, Patent Documents 1 and 2 solve the problem of either the high or low level of the output signal failing to reach the high or low power supply potential by providing capacitance between the output terminal and the gate of one of the transistors. This method of providing capacitance between the output terminal and the gate of one of the transistors is sometimes called bootstrap. On the other hand, transistors having a metal oxide in the channel formation region (also called oxide semiconductor transistors or OS transistors) have attracted attention in recent years. As for OS transistors, n Channel transistors have been put into practical use and have features such as very low off-current, the ability to apply a high voltage between the source and drain (also known as high breakdown voltage), and being thin-film transistors that can be stacked. OS transistors also have features such as less increase in off-current even in high-temperature environments and a large ratio of on-current to off-current even in high-temperature environments, and semiconductor devices constructed using OS transistors are highly reliable. For example, Patent Document 3 describes a semiconductor device having multiple memory cells using OS transistors on a semiconductor substrate on which peripheral circuits such as drive circuits and control circuits are formed, and a DRAM ( An example of using an OS transistor in the memory cell of a Dynamic Random Access Memory is disclosed. For example, Si formed on a single-crystal silicon substrate. A peripheral circuit can be constructed using transistors, and a memory cell using OS transistors can be stacked on top of it. By placing the memory cell using OS transistors on a single-crystal silicon substrate on which the peripheral circuit is formed, the chip area can be r