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JP-2026075595-A - Semiconductor equipment

JP2026075595AJP 2026075595 AJP2026075595 AJP 2026075595AJP-2026075595-A

Abstract

[Problem] To provide a semiconductor device that improves the performance and reliability of its elements. [Solution] The semiconductor device includes a lower insulating pattern 160, a first sheet pattern NS1 in contact with the first surface 160_US of the lower insulating pattern 160, a second sheet pattern NS2 spaced apart in a first direction from the first sheet pattern NS1, a gate structure GS including a gate electrode 120 and a gate insulating film 130, and an inner gate structure GS_INT disposed between the first sheet pattern NS1 and the second sheet pattern NS2, and a bottom insulating spacer 150BSP disposed below the source/drain pattern 150 connected to the first sheet pattern NS1 and the second sheet pattern NS2 and superimposed in a first direction, wherein the first insulating material contained in the bottom insulating spacer 150BP is different from the second insulating material contained in the lower insulating pattern 160, and the thickness of the inner gate structure GS_INT is smaller than the thickness of the lower insulating pattern 160. [Selection Diagram] Figure 2

Inventors

  • 鄭 修 然

Assignees

  • 三星電子株式会社

Dates

Publication Date
20260508
Application Date
20250901
Priority Date
20241022

Claims (10)

  1. A lower insulating pattern including a first surface and a second surface opposite to the first direction, wherein the side wall of the lower insulating pattern connects the first surface and the second surface of the lower insulating pattern, A first sheet pattern that contacts the first surface of the lower insulating pattern, A second sheet pattern is arranged on the first sheet pattern and is spaced apart from the first sheet pattern in a first direction, A gate structure comprising an inner gate structure disposed between the first sheet pattern and the second sheet pattern, extending in a second direction intersecting the first direction, wherein the inner gate structure comprises a gate electrode and a gate insulating film, Source/drain patterns connected to the first sheet pattern and the second sheet pattern, The set includes a bottom insulating spacer positioned below the source/drain pattern in the first direction and superimposed on the source/drain pattern in the first direction, The first insulating material included in the bottom insulating spacer is different from the second insulating material included in the lower insulating pattern. A semiconductor device characterized in that the thickness of the inner gate structure in the first direction is smaller than the thickness of the lower insulating pattern in the first direction.
  2. The invention further includes an inner spacer positioned between the first sheet pattern and the second sheet pattern, The semiconductor device according to claim 1, characterized in that the inner spacer includes the first insulating material.
  3. The semiconductor device according to claim 1, characterized in that the lower insulating pattern includes an air gap.
  4. The semiconductor device according to claim 1, characterized in that the bottom insulating spacer is in contact with the side wall of the lower insulating pattern.
  5. The aforementioned bottom insulating spacer includes a first sub-bottom insulating spacer and a second sub-bottom insulating spacer. The second sub-bottom insulating spacer is positioned between the first sub-bottom insulating spacer and the source/drain pattern. The semiconductor device according to claim 1, characterized in that the second sub-bottom insulating spacer contains the first insulating material.
  6. An upper plate portion and a lower plate portion separated in a first direction, and a lower insulating pattern including a side wall portion connecting the upper plate portion and the lower plate portion, A first sheet pattern is placed on the lower insulating pattern and in contact with the upper plate portion of the lower insulating pattern, A second sheet pattern is arranged on the first sheet pattern and is spaced apart from the first sheet pattern in a first direction, A gate structure comprising an inner gate structure disposed between the first sheet pattern and the second sheet pattern, extending in a second direction intersecting the first direction, wherein the inner gate structure comprises a gate electrode and a gate insulating film, An inner spacer positioned between the first sheet pattern and the second sheet pattern, Source/drain patterns connected to the first sheet pattern and the second sheet pattern, A semiconductor device comprising a bottom insulating spacer disposed in the first direction below the source/drain pattern, superimposed on the source/drain pattern in the first direction, and in contact with the lower insulating pattern.
  7. The lower insulating pattern includes a first surface and a second surface that are opposite to the first direction, The upper plate portion of the lower insulating pattern includes the first surface of the lower insulating pattern. The lower plate portion of the lower insulating pattern includes the second surface of the lower insulating pattern. The height from the second surface of the lower insulating pattern to the uppermost contact point of the bottom insulating spacer is less than or equal to the height from the second surface of the lower insulating pattern to the first surface of the lower insulating pattern. The semiconductor device according to claim 6, characterized in that the uppermost contact is the portion of the bottom insulating spacer closest to the side wall of the lower insulating pattern in a third direction intersecting the first and second directions.
  8. The inner spacer and the lower insulating pattern contain the same insulating material. The semiconductor device according to claim 6, characterized in that the lower insulating pattern contains an insulating material different from the bottom insulating spacer.
  9. The semiconductor device according to claim 6, characterized in that the thickness of the inner gate structure in the first direction is smaller than the thickness of the lower insulating pattern in the first direction.
  10. An air gap, and a lower insulating pattern including a first surface and a second surface opposite to the first direction, A first sheet pattern in contact with the first surface of the lower insulating pattern, A second sheet pattern is arranged on the first sheet pattern and is spaced apart from the first sheet pattern in a first direction, A gate structure comprising an inner gate structure disposed between the first sheet pattern and the second sheet pattern, extending in a second direction intersecting the first direction, wherein the inner gate structure comprises a gate electrode and a gate insulating film, An inner spacer positioned between the first sheet pattern and the second sheet pattern, A first source/drain pattern connected to the first sheet pattern and the second sheet pattern, A second source/drain pattern is connected to the first sheet pattern and the second sheet pattern, and is separated from the first source/drain pattern in a third direction intersecting the first and second directions, A surface wiring line arranged on the first surface of the lower insulating pattern, A rear wiring line arranged on the second surface of the lower insulating pattern, A first bottom insulating spacer is positioned below the source/drain pattern in the first direction and superimposed on the first source/drain pattern in the first direction, A backside source/drain contact that passes through the first bottom insulating spacer and connects the first source/drain pattern and the backside wiring line, A semiconductor device comprising a surface source/drain contact connecting the second source/drain pattern and the surface wiring line.

Description

This invention relates to a semiconductor device, and more particularly to a semiconductor device including an MBCFET® (Multi-Bridge Channel Field Effect Transistor). As one scaling technique to increase the density of semiconductor devices, a multi-gate transistor has been proposed, which involves forming fin- or nanowire-shaped multi-channel active patterns (or silicon bodies) on a substrate and creating gates on the surface of these multi-channel active patterns. Such multi-gate transistors, utilizing a three-dimensional channel, can be easily scaled. Furthermore, they can improve current control capability without increasing the gate length of the multi-gate transistor. Moreover, they can effectively suppress the short-channel effect (SCE), where the channel region potential is affected by the drain voltage. This is an exemplary plan view illustrating a semiconductor device according to several embodiments.This is a cross-sectional view taken along the line A-A in Figure 1.This is a cross-sectional view taken along the line B-B in Figure 1.This diagram illustrates the shape of the lower insulation pattern in Figure 2.This is a magnified view of portion P in Figure 2.This figure illustrates a semiconductor device according to several embodiments.This is a magnified view of portion P in Figure 6.This figure illustrates a semiconductor device according to several embodiments.This figure illustrates a semiconductor device according to several embodiments.This figure illustrates a semiconductor device according to several embodiments.This figure illustrates a semiconductor device according to several embodiments.This is an exemplary plan view illustrating a semiconductor device according to several embodiments.This is a cross-sectional view taken along the line A-A in Figure 12.This is a cross-sectional view taken along the line B-B in Figure 12.This figure illustrates a semiconductor device according to several embodiments.This figure illustrates a semiconductor device according to several embodiments.This figure illustrates a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments.This figure shows an intermediate step for illustrating a method for manufacturing a semiconductor device according to several embodiments. In this specification, terms such as "first," "second," etc., are used to describe various elements and components, but these elements and components are not limited by these terms. These terms are simply used to distinguish one element or c