JP-2026075735-A - Integrated circuits and monitoring systems

JP2026075735AJP 2026075735 AJP2026075735 AJP 2026075735AJP-2026075735-A

Abstract

[Problem] To facilitate verification of software execution behavior even in integrated circuits that include data caches. [Solution] The integrated circuit 1 comprises a processor 10, a memory 12 that holds data defined in software 18 executed by the processor 10, a data cache 11 positioned between the processor 10 and the memory 12, and a recording circuit 13. The data cache 11 temporarily holds write data output from the processor 10 to be written to the memory 12. The recording circuit 13 is connected to a bus 20 between the processor 10 and the data cache 11 and records the write data. [Selection Diagram] Figure 5

Inventors

畑原博文
林英明

Assignees

ルネサスエレクトロニクス株式会社

Dates

Publication Date: 20260511
Application Date: 20241023

Claims (11)

It is an integrated circuit, Processor and A first memory that holds data defined in the software executed by the aforementioned processor, The integrated circuit further comprises a data cache disposed between the processor and the first memory, the data cache temporarily holds write data output from the processor to be written to the first memory, and the integrated circuit further An integrated circuit comprising a recording circuit connected to a bus between the processor and the data cache, for recording the write data.
The aforementioned recording circuit is A buffer for temporarily storing the aforementioned write data, Second memory and The integrated circuit according to claim 1, further comprising a write circuit for writing the write data stored in the buffer to the second memory.
The integrated circuit according to claim 2, wherein the writing circuit writes one or more target data fragments, each written to one or more first addresses in the first memory, from the write data, to the second memory.
The integrated circuit according to claim 3, wherein the writing circuit writes one or more target data fragments to the same addresses as the one or more first addresses in the second memory.
The aforementioned programming circuit is, The one or more first addresses are converted to one or more second addresses in the second memory, In the second memory, write the one or more target data fragments to the one or more second addresses, The integrated circuit according to claim 3, wherein the one or more second addresses are set so that the one or more target data fragments are recorded consecutively from the first address of the second memory.
The integrated circuit according to claim 5, wherein the capacity of the second memory is less than the capacity of the first memory.
The aforementioned recording circuit is A second memory that can be accessed at a faster speed than the first memory, The integrated circuit according to claim 1, further comprising a writing circuit for writing the aforementioned write data to the second memory.
It is a monitoring system, Integrated circuits and Equipped with a monitoring device, The aforementioned integrated circuit is The first processor and A first memory that holds data defined in the software executed by the first processor, The integrated circuit includes a data cache located between the first processor and the first memory, the data cache temporarily holds write data output from the first processor to be written to the first memory, and the integrated circuit further includes Includes a recording circuit connected to the bus between the first processor and the data cache, which records the write data, The monitoring device is A data reader that accesses the recording circuit and reads the written data, A monitoring system including a user interface for visualizing the changes in the values of one or more variables indicated by the aforementioned light data.
The aforementioned recording circuit is A buffer for temporarily storing the aforementioned write data, Second memory and The circuit includes a write circuit that writes the write data stored in the buffer to the second memory, The user interface accepts the designation of one or more target variables from among the multiple variables defined in the software. The monitoring device further includes a second processor that identifies one or more first addresses in the first memory where one or more target data fragments representing one or more target variables are written, The monitoring system according to claim 8, wherein the writing circuit writes one or more target data fragments from the write data to the second memory.
The aforementioned programming circuit is, The one or more first addresses are converted to one or more second addresses in the second memory, In the second memory, write the one or more target data fragments to the one or more second addresses, The monitoring system according to claim 9, wherein the second processor sets one or more second addresses such that one or more target data fragments are recorded consecutively from the first address of the second memory.
The aforementioned one or more target variables include multiple target variables, The one or more target data pieces include a plurality of target data pieces that show the values of the plurality of target variables, The data reader reads the set of multiple target data fragments all at once from the starting address of the second memory. The monitoring system according to claim 10, wherein the second processor analyzes the set and identifies the value of each of the plurality of target variables.

Description

This disclosure relates to integrated circuits and monitoring systems, and is particularly suitable for use in systems that monitor data stored in integrated circuits, such as integrated circuits including data caches. Traditionally, in integrated circuits including a processor and memory, the execution of software by the processor is verified. The processor updates the values of multiple variables by executing the software. The data representing the values of these multiple variables is stored in memory. Therefore, the user verifies the software execution by monitoring the data stored in memory while the processor is executing the software. Furthermore, while the prior art relating to this disclosure has been described above based on general technical information known to the applicant, to the best of the applicant's recollection, the applicant does not possess any prior art information that should have been disclosed before filing the application. This figure shows an example of the overall configuration of the monitoring system according to the embodiment.This is a diagram showing the configuration of a monitoring system related to a reference configuration.This diagram illustrates data monitoring using a monitoring device.This flowchart shows an example of the control process flow of an integrated circuit related to the reference form.This is a block diagram illustrating the internal configuration of the monitoring system according to this embodiment.This figure shows the configuration of Example 1 of the monitoring system according to this embodiment.This figure shows the data storage status in Example 1.This figure shows an example of the first table.This figure shows the configuration of Example 2 of the monitoring system according to this embodiment.This figure shows the data storage status in Example 2.This figure shows an example of the second table.This diagram illustrates the effect of reducing the amount of communication between the monitoring device and the monitor RAM.This diagram shows the configuration of Example 3 of the monitoring system according to this embodiment. The embodiments of this disclosure will be described in detail below with reference to the drawings. Parts identical or corresponding to each other will be denoted by the same reference numerals, and their descriptions will not be repeated. <Overall configuration of the monitoring system> Figure 1 is a diagram showing an example of the overall configuration of a monitoring system according to an embodiment. As shown in Figure 1, the monitoring system 100 comprises an integrated circuit 1 and a monitoring device 3. The integrated circuit 1 is a semiconductor integrated circuit including a processor and memory. The integrated circuit 1 includes, for example, a System-on-a-chip (SoC) or a Microcontroller Unit (MCU). The integrated circuit 1 is mounted, for example, on a substrate 4. The substrate 4 is incorporated into a device to which the control functions realized by the integrated circuit 1 are applied. The device may include, for example, electronic equipment, production equipment, and vehicles. The processor of the integrated circuit 1 executes software for realizing the control functions. The monitoring device 3 assists in verifying the execution of the software in the integrated circuit 1. The user uses the monitoring device 3 to verify the execution of the software in the integrated circuit 1. Once it is confirmed that there are no problems with the execution of the software in the integrated circuit 1, the monitoring device 3 is removed from the integrated circuit 1. The monitoring device 3 monitors the data held in the integrated circuit 1 to support the verification of the software execution operation in the integrated circuit 1. The monitoring device 3 includes a debug interface 30 connected to the integrated circuit 1, a data reader 31 for reading the data held in the integrated circuit 1, and an information processing device 32. The information processing device 32 is a computer with a general-purpose architecture. The information processing device 32 includes, for example, personal computers, tablets, and smartphones. The information processing device 32 visualizes information indicated by data read by the data reader 31. For example, the information processing device 32 visualizes the changes in the values of variables defined in the software incorporated into the integrated circuit 1. Specifically, the information processing device 32 displays a graph or time-series numerical data representing the changes in the variable values. The user verifies the execution operation of the software in the integrated circuit 1 by checking the changes in the variable values. <Problems with the reference format> Before providing a detailed description of the monitoring system 100 according to this embodiment, we will first explain the problems of a monitoring system according to a reference embodiment with reference to Figures