JP-2026075763-A - Semiconductor wafer manufacturing method

Abstract

[Problem] To provide a semiconductor wafer manufacturing method that can improve the uniformity of the etching removal amount in the wafer radial direction in single-wafer spin etching. [Solution] The semiconductor wafer manufacturing method according to the present invention is a semiconductor wafer manufacturing method comprising slicing a semiconductor single crystal ingot (crystal block) into a wafer shape using a wire saw, removing cutting damage formed on the slice surface by lapping, and processing the surface of the wafer to a flat mirror surface, and further comprising a grinding step of grinding each surface of the wafer after lapping under different grinding conditions to adjust the warp shape of the wafer, and a single-wafer etching step of performing a first etching treatment on the concave surface of the wafer after grinding, and then performing a second etching treatment on the convex surface. [Selection Diagram] Figure 4

Inventors

• 堀川 智之

Assignees

• グローバルウェーハズ・ジャパン株式会社

Dates

Publication Date

20260511

Application Date

20241023

Claims (7)

1. A method for manufacturing a semiconductor wafer, comprising cutting a semiconductor single crystal ingot to obtain a crystal block, slicing it into wafers using a wire saw, removing cutting damage formed on the sliced surface by lapping, and then processing the surface of the wafer to a flat, mirror-like surface, A grinding process is performed to adjust the warp shape of the wafer by grinding each surface of the wafer after the lapping process under different grinding conditions, A single-wafer etching process comprising: performing a first etching process on the concave surface of the wafer after the grinding process; and, after the completion of the first etching process, inverting the etched surface and performing a second etching process on the convex surface; including, A method for manufacturing semiconductor wafers, characterized by the following features.
2. In the grinding process, the grinding conditions are as follows: Each surface of the wafer is ground with a grinding wheel of a different abrasive particle size. The method for manufacturing a semiconductor wafer according to claim 1.
3. In the grinding process, the wafer's curvature is adjusted so that the amount of curvature is greater than that of the wafer after slicing with a wire saw. The method for manufacturing a semiconductor wafer according to claim 1.
4. As for the grinding conditions, when grinding each side of the wafer in single-sided grinding, the opposite side of the surface to be ground is fixed by suction while grinding. The method for manufacturing a semiconductor wafer according to claim 1.
5. In the single-wafer etching process, the concave surface to be etched first and the convex surface to be etched second are processed at different wafer rotation speeds. The method for manufacturing a semiconductor wafer according to claim 1.
6. The amount of warpage of the wafer after slicing with a wire saw is reduced to 30 μm or less. The method for manufacturing a semiconductor wafer according to claim 1.
7. The amount of warpage of the wafer after grinding is set to 50 μm to 300 μm by performing the aforementioned grinding process. The method for manufacturing a semiconductor wafer according to claim 1.

Description

This invention relates to a method for manufacturing semiconductor wafers for semiconductor substrates. In the semiconductor wafer manufacturing process, after obtaining a semiconductor single crystal ingot grown by the CZ method, the ingot is sliced into wafers using a wire saw or the like (see Patent Document 1) (slicing step). Then, the wafer is ground (see Patent Document 2) to remove cutting damage formed during slicing and to adjust flatness and surface roughness (grinding step). Finally, single-wafer spin etching removes processing damage introduced during grinding (single-wafer etching step), and lastly, the surface of the resulting wafer is mirror-polished (polishing step). On the other hand, when a semiconductor single-crystal ingot is sliced with a wire saw, the sliced surface (wafer surface) contains cutting damage, such as steps formed by the reciprocating wire during slicing and a fractured layer formed by the free abrasive particles processed by the wire saw. Therefore, it is necessary to remove these while processing to create a flat, mirror-like surface. However, since the thickness of these steps and fractured layers is generally around 10-20 μm, it is difficult to remove them solely with single-wafer spin etching. Therefore, in conventional semiconductor wafer manufacturing processes, grinding is performed on the wafer after slicing with a wire saw. This reduces cutting damage, and as a result, the amount of material removed by single-wafer spin etching can be reduced. Japanese Patent Publication No. 2001-1335Japanese Patent Publication No. 2005-262327 Figure 1 is a flowchart showing the method for manufacturing a semiconductor wafer according to the present invention.Figure 2 is a schematic diagram showing an example of the slicing process.Figure 3 shows an example of the amount of warpage in relation to grinding damage for each abrasive particle size.Figure 4 schematically shows the change in wafer shape during the single-wafer etching process. The following describes in detail, with reference to the drawings, an embodiment of the semiconductor wafer manufacturing method according to the present invention. However, the present invention is not limited to this embodiment. <Method of manufacturing semiconductor wafers> The semiconductor wafer manufacturing method of this embodiment includes a slicing step of cutting a wafer from a semiconductor single crystal ingot (crystal block), a lapping step of removing cutting damage formed during slicing, a grinding step of adjusting the wafer's warp shape by grinding both sides of the wafer by single-sided grinding, a single-wafer etching step of removing processing damage introduced in the grinding step, and a polishing step of performing mirror polishing on the surface of the wafer after the etching process, thereby removing cutting damage (such as a crushed layer) formed on the wafer by the slicing step and achieving a mirror finish. The semiconductor wafer manufacturing method of this embodiment will be explained in more detail below using the drawings. Figure 1 is a flowchart showing the semiconductor wafer manufacturing method of this embodiment, and Figure 2 is a schematic diagram showing an example of the slicing process. First, a semiconductor single crystal ingot grown by the CZ method is obtained. Then, the resulting crystal block 1 is sliced into wafers using a wire saw (Step S1: Slicing Process). At this stage, it is preferable to keep the amount of warping of each wafer generated by the wire saw to 30 μm or less. In this embodiment, for example, the amount of warping of each wafer is kept to 30 μm or less by stably maintaining the processing heat. If the amount of warping exceeds 30 μm, it becomes difficult to control the warp shape in the grinding process described later, which is undesirable. When the crystal block 1 is sliced (cut) into wafers using a wire saw, the sliced surface (wafer surface) contains cutting damage, including steps formed by the reciprocating wire during slicing and a fractured layer formed by the processing of loose abrasive particles by the wire saw. Therefore, after the slicing process, these steps and fractured layers are removed by lapping (Step S2: Lapping process). Furthermore, when the crystal block 1 is sliced into wafers using a wire saw, as described above, each wafer obtained by slicing will exhibit warping. The shape of this warping (convex shape) varies due to thermal deformation of the crystal block 1, the wire guide, and the wire saw itself during cutting with the wire and slurry (free abrasive particles). Therefore, not all wafers will have a uniform warping orientation (upward or downward convex) and a uniform warp magnitude (Warp). In other words, the magnitude of this warp varies depending on the slicing position of the crystal block 1 (see Figure 2). Also, the orientation of the warping shape may be symmetrical with respect to the center of the crystal block 1. In such cases, even if wafer