JP-2026075803-A - Semiconductor memory device, recording head, and data writing method

Abstract

[Problem] To provide a semiconductor memory device capable of 2-bit writing that can suppress a decrease in productivity and the occurrence of write errors. [Solution] The semiconductor memory device 10 has a first antifuse element 1 and a second antifuse element 2, and a supply line 9a from one power source (9) branches off and is connected to the first and second antifuse elements, respectively. The control circuit 7 alternately applies voltage to the first antifuse element 1 and to the second antifuse element 2. [Selection Diagram] Figure 1

Inventors

• 中野 俊男
• 下山 洋司
• 根岸 俊雄

Assignees

• キヤノン株式会社

Dates

Publication Date

20260511

Application Date

20241023

Claims (12)

1. A semiconductor memory device having a first antifuse element and a second antifuse element, wherein a supply line from one power source branches off and is connected to the first and second antifuse elements, A semiconductor memory device characterized by having a control circuit that alternately applies a voltage to the first antifuse element and a voltage to the second antifuse element.
2. The semiconductor memory device according to claim 1, characterized in that the control circuit receives a pulse signal consisting of a rectangular wave with a certain width as input, applies a voltage to the first antifuse element when the pulse signal is at a high level, and applies a voltage to the second antifuse element when the pulse signal is at a low level.
3. A first switch element connected in series with the first antifuse element, The second antifuse element is connected in series with a second switch element, The power supply is connected to the ground potential terminal via the first antifuse element and the first switch element, and is also connected to the ground potential terminal via the second antifuse element and the second switch element. The semiconductor memory device according to claim 2, characterized in that the control circuit turns the first switch element on and the second switch element off when the pulse signal is at a high level, and turns the first switch element off and the second switch element on when the pulse signal is at a low level.
4. The first switching element is provided between the first antifuse element and the ground potential terminal. The semiconductor memory device according to claim 3, characterized in that the second switching element is provided between the second antifuse element and the ground potential terminal.
5. The first switching element is provided between the power supply and the first antifuse element. The semiconductor memory device according to claim 3, characterized in that the second switching element is provided between the power supply and the second antifuse element.
6. The first switching element is provided between the first antifuse element and the ground potential terminal. The semiconductor memory device according to claim 3, characterized in that the second switching element is provided between the power supply and the second antifuse element.
7. The first switching element is provided between the power supply and the first antifuse element. The semiconductor memory device according to claim 3, characterized in that the second switching element is provided between the second antifuse element and the ground potential terminal.
8. The semiconductor memory device according to claim 2, characterized in that the duty cycle of the pulse signal is 50%.
9. The device has a shift register that outputs a selection signal for selecting a pair of first and second antifuse elements (2 bits) from among a plurality of first and a plurality of second antifuse elements. The semiconductor memory device according to claim 1, wherein the control circuit sequentially selects the pair of first and second antifuse elements from among the plurality of first and second antifuse elements as targets to which voltage should be applied, based on the selection signal.
10. It has an element substrate on which a recording element for discharging liquid is formed, The recording head is characterized in that the element substrate includes the semiconductor memory device described in any one of claims 1 to 9.
11. The recording head according to claim 10, characterized in that it stores data for discharging the liquid in the semiconductor storage device.
12. A method for writing data to a semiconductor memory device having a plurality of first antifuse elements and a plurality of second antifuse elements, wherein a supply line from a single power source branches off and is connected to each of the first and second antifuse elements, From among the plurality of first antifuse elements and the plurality of second antifuse elements, select a pair of first and second antifuse elements that are equivalent to two bits. A data writing method characterized by alternately applying voltage to the pair of first and second antifuse elements.

Description

This invention relates to a semiconductor memory device equipped with an antifuse element, a recording head, and a data writing method. As a semiconductor memory device, there are OTP (One-Time Programmable) memories that use polyfuse elements and antifuse elements. While antifuse elements offer more stable write states compared to polyfuse elements, their write cycle time is longer (for example, about 10 times longer), which can reduce productivity. Therefore, in semiconductor memory devices equipped with antifuse elements, 2-bit writing is being considered to simultaneously write to 2-bit antifuse elements connected to a single power supply, thereby increasing the cycle time. Patent Document 1 describes a semiconductor memory device equipped with an antifuse element. In this semiconductor memory device, a memory cell array containing memory cells with antifuse elements is divided into two memory banks. Two boost circuits generate write and read voltages supplied to the antifuse elements in each memory bank. During writing, one bit line is selected for each memory bank to be written to simultaneously. Writing is performed simultaneously to the selected antifuse elements in each memory bank. Japanese Patent Publication No. 2010-170609 This is a schematic diagram showing the configuration of a semiconductor memory device according to the first embodiment of the present invention.This timing diagram shows the relationship between the pulse signal, the gate voltage of the first switch element, and the voltage applied to the first antifuse element.This timing diagram shows the relationship between the pulse signal, the gate voltage of the second switch element, and the voltage applied to the second antifuse element.This timing diagram shows the relationship between the pulse signal, the voltage applied to the first antifuse element, and the voltage applied to the second antifuse element.This is a timing diagram for 2-bit writing in a comparative example.This is a schematic diagram showing the configuration of a semiconductor memory device according to a second embodiment of the present invention.This is a perspective view of a recording head equipped with the semiconductor memory device of the present invention.This is a schematic diagram illustrating the configuration of the element substrate. The embodiments of the present invention will be described in detail below with reference to the drawings. However, these embodiments are merely illustrative and are not intended to limit the scope of the present invention to these embodiments. (First embodiment) Figure 1 is a schematic diagram showing the configuration of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device 10 of this embodiment has a first antifuse element 1, a second antifuse element 2, and a control circuit 7. The semiconductor memory device 10 is configured such that a supply line 9a from a single power supply (power supply circuit 9) branches off and is connected to the first and second antifuse elements 1 and 2, respectively, and voltage is selectively applied to the first and second antifuse elements 1 and 2. The control circuit 7 alternately applies voltage to the first antifuse element 1 and the second antifuse element 2. Two bits are written by applying voltage to the first and second antifuse elements 1 and 2. As shown in Figure 1, the first antifuse element 1 consists of n first antifuse elements 11 to 1n , and the second antifuse element 2 consists of n second antifuse elements 21 to 2n . These first antifuse elements 11 to 1n and the second antifuse elements 21 to 2n constitute a 2n-bit memory. n can be set appropriately according to the data to be written. The first antifuse elements 11 to 1n and the second antifuse elements 21 to 2n all have the same structure, and the first and second antifuse elements are arranged alternately from left to right in the drawing. The first antifuse elements 13 to 1n and the second antifuse elements 23 to 2n are not shown. One end of each of the first antifuse elements 11 to 1n and the second antifuse elements 21 to 2n is connected to a supply line 9a from the power supply circuit 9. The first switch element 31 is connected in series with the first antifuse element 11. Similarly, the first switch elements 32 to 3n are connected in series with the first antifuse elements 12 to 1n . The second switch element 41 is connected in series with the second antifuse element 21. Similarly, the second switch elements 42 to 4n are connected in series with the second antifuse elements 32 to 2n . The other ends of each of the first antifuse elements 11 to 1n are connected to the GND terminal (ground potential terminal) via the first switch elements 31 to 3n . The other ends of each of the second antifuse elements 21 to 1n are connected to the GND terminal (ground potential terminal) via the second switch elements 41 to 4n . The first switching elements 31