JP-2026075811-A - Semiconductor equipment and isolation switches

Abstract

[Problem] To stabilize the potential of the semiconductor substrate in a semiconductor device. [Solution] The semiconductor device 10 includes a switch circuit chip 90 and a control circuit chip 80 mounted on a first die pad 101, a first conductive bonding material SD1 that bonds the first die pad 101 and the switch circuit chip 90, and a second conductive bonding material SD2 that bonds the first die pad 101 and the control circuit chip 80. The switch circuit chip 90 includes a first semiconductor substrate 91 bonded to the first die pad 101 by the first conductive bonding material SD1, and a first transistor 51 and a second transistor 52 whose sources are connected to each other. Both the first transistor 51 and the second transistor 52 are high electron mobility transistors containing nitride semiconductors. The sources of the first transistor 51 and the second transistor 52 are electrically connected to the first die pad 101 through the control circuit chip 80. [Selection Diagram] Figure 9

Inventors

• 齊藤 弘治
• 名手 智

Assignees

• ローム株式会社

Dates

Publication Date

20260511

Application Date

20241023

Claims (20)

1. First die pad and A switch circuit chip mounted on the first die pad, A control circuit chip mounted on the first die pad, which includes a control circuit for controlling the drive of the switch circuit chip, A first conductive bonding material for joining the first die pad and the switch circuit chip, A second conductive bonding material that joins the first die pad and the control circuit chip, A first terminal and a second terminal are arranged spaced apart from the first die pad, A sealing resin that at least seals the first conductive bonding material, the second conductive bonding material, the switch circuit chip, and the control circuit chip, while at least partially exposing both the first terminal and the second terminal, Equipped with, The aforementioned switch circuit chip is The first chip surface and The back surface of the first chip, which is opposite to the front surface of the first chip, A first semiconductor substrate which constitutes the back surface of the first chip and is bonded to the first die pad by the first conductive bonding material, An insulating layer provided on the first semiconductor substrate, A first transistor and a second transistor are provided between the insulating layer and the surface of the first chip in the thickness direction of the switch circuit chip, with their sources connected to each other. Includes, Both the first transistor and the second transistor are high electron-mobility transistors containing nitride semiconductors. A semiconductor device in which the source of the first transistor and the source of the second transistor are electrically connected to the first die pad through the control circuit chip.
2. The aforementioned control circuit chip is The second chip surface and The back surface of the second chip, which is opposite to the front surface of the second chip, A second semiconductor substrate which constitutes the back surface of the second chip and is bonded to the first die pad by the second conductive bonding material, The first output pad exposed from the surface of the second chip, The second output pad is electrically connected to the second semiconductor substrate and is exposed from the surface of the second chip, Includes, The aforementioned switch circuit chip is A first input pad is exposed from the surface of the first chip and electrically connected to both the gate of the first transistor and the gate of the second transistor, A second input pad is exposed from the surface of the first chip and electrically connected to the source of the first transistor and the source of the second transistor, Includes, A first connecting member that connects the first output pad and the first input pad, A second connecting member that connects the second output pad and the second input pad, A semiconductor device according to claim 1, comprising:
3. Including a third terminal integrated with the first die pad, The semiconductor device according to claim 1, wherein a portion of the third terminal is exposed from the sealing resin.
4. The semiconductor device according to claim 3, wherein the third terminal is located on the side of the first die pad where the first terminal and the second terminal are located.
5. The semiconductor device according to claim 4, wherein the third terminal is provided between the first terminal and the second terminal.
6. The semiconductor device according to claim 1, wherein the thickness of the insulating layer is thinner than the thickness of the first semiconductor substrate.
7. The semiconductor device according to claim 1, wherein the insulating layer is made of a material containing AlN.
8. The aforementioned switch circuit chip is A buffer layer provided on the insulating layer, An electron transport layer provided on the buffer layer, Includes, The buffer layer is made of a material containing AlGaN, The electron transport layer includes a doped layer made of a material containing GaN doped with acceptor-type impurities, The semiconductor device according to claim 7, wherein the doped layer is provided in the electron transport layer closer to the buffer layer.
9. The aforementioned switch circuit chip is An electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a band gap larger than that of the electron transport layer, A source electrode provided on the electron supply layer, A first drain electrode and a second drain electrode are provided on the electron supply layer and are arranged spaced apart on both sides of the source electrode, A gate electrode is provided on the electron supply layer and, in a plan view, is positioned between the source electrode and the first drain electrode, and between the source electrode and the second drain electrode, The semiconductor device according to claim 8, including
10. The semiconductor device according to claim 9, wherein the switch circuit chip includes a gate layer interposed between the gate electrode and the electron supply layer.
11. A second die pad is positioned at a distance from the first die pad, The insulating chip mounted on the second die pad, A relay connecting member that electrically connects the insulating chip and the control circuit chip, Furthermore, The semiconductor device according to claim 1, wherein the sealing resin seals the insulating chip and the relay connection member.
12. The drive circuit chip mounted on the second die pad, An intermediate connecting member that connects the insulating chip and the drive circuit chip, Furthermore, The semiconductor device according to claim 11, wherein the sealing resin seals the drive circuit chip and the intermediate connecting member.
13. The semiconductor device according to claim 12, wherein the insulating chip is disposed between the drive circuit chip and the control circuit chip in the arrangement direction of the first die pad and the second die pad.
14. The aforementioned insulating chip is The third chip surface and The back surface of the third chip, opposite to the front surface of the third chip, The third semiconductor substrate that constitutes the back surface of the aforementioned third chip, A third insulator provided on the third semiconductor substrate, The first insulating element provided on the third insulator, A second insulating element is provided on the third insulating element and is positioned opposite the first insulating element, The semiconductor device according to claim 11, including
15. A second die pad is positioned at a distance from the first die pad, The drive circuit chip mounted on the second die pad, A chip connecting member that connects the control circuit chip and the drive circuit chip, Furthermore, The drive circuit chip includes a drive circuit that outputs a signal to the control circuit chip. The aforementioned control circuit is Rectifier circuit and A gate voltage control circuit electrically connected to the rectifier circuit, Includes, The aforementioned control circuit chip is A first insulating element electrically connected to the aforementioned drive circuit, A second insulating element is positioned opposite the first insulating element and electrically connected to the rectifier circuit, Includes, The semiconductor device according to claim 1, wherein the sealing resin seals the drive circuit chip and the chip connecting member.
16. A second die pad is positioned at a distance from the first die pad, The drive circuit chip mounted on the second die pad, A chip connecting member that connects the control circuit chip and the drive circuit chip, Furthermore, The aforementioned drive circuit chip is First insulating element and A second insulating element is positioned opposite the first insulating element, A drive circuit that outputs a signal to the first insulating element, Includes, The control circuit chip includes a gate voltage control circuit and a rectifier circuit as the control circuit. The semiconductor device according to claim 1, wherein the sealing resin seals the drive circuit chip and the chip connecting member.
17. Power terminals and signal terminals are arranged separately from the second die pad, The ground terminal integrated with the second die pad, A power connection member that connects the drive circuit chip and the power terminal, A signal connection member that connects the drive circuit chip and the signal terminal, Furthermore, The semiconductor device according to claim 12, wherein the sealing resin seals the power connection member and the signal connection member, and partially seals the power terminal, the signal terminal, and the ground terminal.
18. The semiconductor device according to claim 17, wherein the power terminal, the signal terminal, and the ground terminal are arranged on the opposite side of the second die pad from the first die pad.
19. The aforementioned switch circuit chip is A first power supply pad is exposed from the surface of the first chip and is electrically connected to the drain of the first transistor, A second power supply pad is exposed from the surface of the first chip and electrically connected to the drain of the second transistor, Includes, A first power connection member that connects the first power pad and the first terminal, A second power connection member that connects the second power pad and the second terminal, Equipped with, The semiconductor device according to claim 1, wherein the sealing resin seals both the first power connection member and the second power connection member.
20. A semiconductor device according to any one of claims 1 to 19, A power supply circuit is electrically connected to the semiconductor device and configured to supply an operating voltage to the semiconductor device. A signal generation circuit is electrically connected to the semiconductor device and configured to output a control signal for controlling a load electrically connected to the semiconductor device. An insulated switch equipped with this feature.

Description

This disclosure relates to semiconductor equipment and isolation switches. Patent Document 1 discloses a bidirectional switch in which the source of a first MOSFET is connected to the source of a second MOSFET. This bidirectional switch includes a first drain terminal connected to the drain electrode of the first MOSFET, a first gate terminal connected to the gate electrode of the first MOSFET, a second drain terminal connected to the drain electrode of the second MOSFET, a second gate terminal connected to the gate electrode of the second MOSFET, and a common source terminal connecting the source electrode of the first MOSFET and the source electrode of the second MOSFET. Japanese Patent Publication No. 2018-160661 [overview] Incidentally, when a high-electron-mobility transistor (HEMT) made of nitride semiconductor material is used as the switching circuit for a bidirectional switch, stabilization of the potential of the semiconductor substrate in the HEMT is required. A semiconductor device according to one aspect of the present disclosure comprises: a first die pad; a switch circuit chip mounted on the first die pad; a control circuit chip mounted on the first die pad and including a control circuit for controlling the drive of the switch circuit chip; a first conductive bonding material for joining the first die pad and the switch circuit chip; a second conductive bonding material for joining the first die pad and the control circuit chip; a first terminal and a second terminal arranged separately from the first die pad; and a sealing resin that at least seals the first conductive bonding material, the second conductive bonding material, the switch circuit chip, and the control circuit chip, while at least partially exposing both the first terminal and the second terminal, wherein the switch circuit The chip includes a first chip surface, a first chip back surface opposite to the first chip surface, a first semiconductor substrate constituting the first chip back surface and bonded to the first die pad by the first conductive bonding material, an insulating layer provided on the first semiconductor substrate, and a first transistor and a second transistor provided between the insulating layer and the first chip surface in the thickness direction of the switch circuit chip, with their sources connected to each other. Both the first and second transistors are high electron-mobility transistors containing nitride semiconductors, and the sources of the first and second transistors are electrically connected to the first die pad through the control circuit chip. Figure 1 is a schematic circuit diagram of an insulating switch equipped with an exemplary semiconductor device according to the first embodiment.Figure 2 is a schematic plan view of the semiconductor device shown in Figure 1.Figure 3 is a schematic cross-sectional view of the semiconductor device shown in Figure 2.Figure 4 is a schematic cross-sectional view of an insulating chip in a semiconductor device.Figure 5 is a schematic cross-sectional view of a portion of the insulating chip in a semiconductor device that differs from the portion shown in Figure 4.Figure 6 is a schematic cross-sectional view illustrating the configuration of the control circuit chip shown in Figure 3.Figure 7 is a schematic plan view showing an enlarged portion of the internal structure of the switch circuit chip shown in Figure 3.Figure 8 is a schematic cross-sectional view obtained by cutting the switch circuit chip along the F8-F8 line in Figure 7.Figure 9 is a schematic, enlarged view of the control circuit chip, switch circuit chip, and surrounding area in the semiconductor device shown in Figure 3.Figure 10 is a schematic plan view of an exemplary semiconductor device according to the second embodiment.Figure 11 is a schematic cross-sectional view illustrating the configuration of the control circuit chip shown in Figure 10.Figure 12 is a schematic circuit diagram of an insulating switch equipped with an exemplary semiconductor device according to the third embodiment.Figure 13 is a schematic plan view of the semiconductor device shown in Figure 12.Figure 14 is a schematic cross-sectional view of the drive circuit chip in the modified semiconductor device.Figure 15 is a schematic cross-sectional view of the insulating chip in the modified semiconductor device.Figure 16 is a schematic plan view of the modified semiconductor device. [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of this disclosure will be described with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting this disclosure. The following detai