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JP-2026075854-A - Semiconductor device and method for manufacturing a semiconductor device

JP2026075854AJP 2026075854 AJP2026075854 AJP 2026075854AJP-2026075854-A

Abstract

[Problem] The objective is to provide a technology that can improve the insulation between the upper electrode and the lower electrode. [Solution] The semiconductor device comprises a semiconductor substrate and a first trench structure. The first trench structure includes a lower electrode provided on the lower part of a trench provided on the first main surface of the semiconductor substrate via a first insulating film, and an upper electrode provided on the upper part of the trench via a third insulating film, insulated from the lower electrode by a second insulating film. The ratio of crystal orientations with (111) plane orientations is higher for the lower electrode than for the upper electrode. [Selection Diagram] Figure 1

Inventors

  • 迫 紘平
  • 梅田 浩司
  • 小西 和也

Assignees

  • 三菱電機株式会社

Dates

Publication Date
20260511
Application Date
20241023

Claims (17)

  1. A semiconductor substrate having a first main surface, The semiconductor substrate comprises a first trench structure provided on the first main surface side, The first trench structure is A lower electrode is provided on the lower part of a trench provided on the first main surface of the semiconductor substrate via a first insulating film, It includes an upper electrode that is insulated from the lower electrode by a second insulating film and is provided on the upper part of the trench via a third insulating film, The upper electrode is electrically connected to the first gate electrode. A semiconductor device in which the ratio of crystal orientations with a (111) plane orientation is higher for the lower electrode than for the upper electrode.
  2. A semiconductor device according to claim 1, A semiconductor device in which the average grain size of the crystals is larger in the lower electrode than in the upper electrode.
  3. A semiconductor device according to claim 1, A semiconductor device having an average particle size of 0.5 μm or more and 4.0 μm or less for the lower electrode.
  4. A semiconductor device according to claim 1, A semiconductor device having an average particle size of 0.8 μm or more and 4.0 μm or less for the lower electrode.
  5. A semiconductor device according to claim 1, A semiconductor device wherein the average particle size of the lower electrode is 1.1 times or more and 4.0 μm or less than or equal to the average particle size of the upper electrode.
  6. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the concentration of impurities is higher in the lower electrode than in the upper electrode.
  7. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the concentration of impurities is lower in the lower electrode than in the upper electrode.
  8. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is thinner than the thickness of the third insulating film in contact with the side of the upper electrode.
  9. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is greater than the thickness of the third insulating film in contact with the side of the upper electrode.
  10. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the volume of the lower electrode is smaller than the volume of the upper electrode.
  11. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the volume of the lower electrode is larger than the volume of the upper electrode.
  12. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the lower electrode is electrically connected to the first gate electrode.
  13. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the lower electrode is electrically connected to a second gate electrode having a different voltage control from the first gate electrode.
  14. A semiconductor device according to any one of claims 1 to 5, A semiconductor device comprising a second trench structure corresponding to the first trench structure, wherein the upper electrode is electrically connected to the emitter electrode and the lower electrode is electrically connected to the first gate electrode.
  15. A semiconductor device according to any one of claims 1 to 5, A semiconductor device further comprising a dummy trench structure on the first main surface side of the semiconductor substrate.
  16. A step of preparing a semiconductor substrate having a first main surface on which trenches are provided, The steps include forming a conductive member on the lower part of the trench via a first insulating film, The process involves thermally oxidizing the upper part of the conductive member to form a second insulating film from the upper part of the conductive member, and forming a lower electrode from the remaining part of the conductive member. The process includes the step of forming an upper electrode, which is insulated from the lower electrode by the second insulating film, on the upper part of the trench via a third insulating film, The upper electrode is connected to the first gate electrode, A method for manufacturing a semiconductor device, wherein the ratio of crystal orientations being (111) plane orientations is higher for the lower electrode than for the upper electrode.
  17. A method for manufacturing a semiconductor device according to claim 16, A method for manufacturing a semiconductor device, comprising forming the third insulating film by thermal oxidation of the upper part of the trench when forming the second insulating film by thermal oxidation.

Description

This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. In recent years, semiconductor devices have been proposed that include upper and lower electrodes insulated from each other within a trench in order to reduce switching losses (for example, Patent Document 1). Japanese Patent Publication No. 2006-324570 This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1.This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1.(a) to (c) are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment 1.This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 3.This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 3.This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 4.This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2.This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 3. The embodiments will be described below with reference to the attached drawings. The features described in each embodiment below are illustrative, and not all features are necessarily required. Furthermore, in the following descriptions, similar components in multiple embodiments are denoted by the same or similar reference numerals, and the different components are primarily described. Also, in the following descriptions, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the actual positions and directions in implementation. Furthermore, a higher concentration in one part than in another may mean, for example, that the average concentration in one part is higher than the average concentration in the other part. Conversely, a lower concentration in one part than in another may mean, for example, that the average concentration in one part is lower than the average concentration in the other part. Also, although the following descriptions assume that the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may be p-type and the second conductivity type may be n-type. <Embodiment 1> Figures 1 and 2 are cross-sectional views showing the configuration of a semiconductor device according to this first embodiment. In the following description, a configuration in which the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) will be used as an example, but it is not limited to this. The semiconductor device may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an RC-IGBT (Reverse Conducting IGBT) having an IGBT region where an IGBT is provided and a diode region where an SBD (Schottky Barrier Diode) and a PND (PN junction diode) are provided. The semiconductor device shown in Figure 1 comprises a semiconductor substrate, a first trench structure 11, an interlayer insulating film 21, an emitter electrode 22, and a collector electrode 23. The semiconductor substrate includes an n - type drift layer 1, an n-type carrier storage layer 2, a p-type base layer 3, an n + -type source layer 4, an n-type buffer layer 5, and a p-type collector layer 6. The semiconductor substrate has a first main surface corresponding to the upper end of the source layer 4 and a second main surface corresponding to the lower end of the collector layer 6. The semiconductor substrate may be composed of a conventional semiconductor wafer or an epitaxial growth layer. Furthermore, the semiconductor substrate may be composed of conventional silicon (Si), or of a wide - bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide ( Ga₂O₃ ), or diamond. When the semiconductor substrate is composed of a wide-bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages, and faster switching speeds of the semiconductor device become possible. Next, we will describe each layer of the semiconductor substrate. A carrier storage layer 2 with a higher n-type impurity concentration than that of the drift layer 1 is provided on the first main surface side of the drift layer 1. A base layer 3 is provided on the first main surface side of the carrier storage layer 2. A source layer 4 with a higher n-type impurity concentration than that of the carrier storage layer 2 is provided on the first main surface side of the base layer 3. As described above, the semiconductor substrate according to this embodiment 1 has a drift layer 1, a carrier storage layer 2, a base layer 3, and a source layer 4 arranged in this order toward the first main surface. On the other hand, the s