JP-2026075993-A - Semiconductor device and method for manufacturing the same

JP2026075993AJP 2026075993 AJP2026075993 AJP 2026075993AJP-2026075993-A

Abstract

[Problem] To improve the performance of semiconductor devices. [Solution] Chip mounting section TAB1 and chip mounting section TAB3 are electrically connected via a resistor R1, and chip mounting section TAB2 and chip mounting section TAB3 are electrically connected via a resistor R2. [Selection Diagram] Figure 5

Inventors

中柴康隆
波多俊幸

Assignees

ルネサスエレクトロニクス株式会社

Dates

Publication Date: 20260511
Application Date: 20241023

Claims (18)

A first chip mounting section to which a first potential is supplied, A first semiconductor chip disposed on the first chip mounting section, A second chip mounting section to which a second potential higher than the first potential is supplied, A second semiconductor chip is placed on the second chip mounting section, A third chip mounting section is electrically connected to the first chip mounting section via a first resistive element and electrically connected to the second chip mounting section via a second resistive element, An isolator chip positioned on the third chip mounting section, Equipped with, The isolator chip is Lower conductor section, A first upper conductor portion is formed above the lower conductor portion via an insulating layer and is electrically connected to the first semiconductor chip, A second upper conductor portion is formed above the lower conductor portion via the insulating layer, is arranged separately from the first upper conductor portion, and is electrically connected to the second semiconductor chip, A semiconductor device having
In the semiconductor device described in claim 1, The lower conductor portion and the first upper conductor portion are components of the first transformer. The lower conductor portion and the second upper conductor portion are components of the second transformer.
In the semiconductor device described in claim 1, The aforementioned lower conductor portion is the lower electrode, The first upper conductor portion is the first upper electrode, The second upper conductor portion is the second upper electrode.
In the semiconductor device described in claim 1, The first resistive element is a first chip resistor, The second resistive element is a second chip resistor.
In the semiconductor device according to claim 4, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first chip resistor and the second chip resistor is defined as the second direction, the first direction and the second direction are parallel to each other.
In the semiconductor device described in claim 5, The first chip mounting portion has a first surface on which the first semiconductor chip is placed, The second chip mounting portion has a second surface on which the second semiconductor chip is arranged. The third chip mounting portion has a third surface on which the isolator chip is arranged. The first chip resistor is arranged across the first surface and the third surface, The second chip resistor is arranged across the second surface and the third surface.
In the semiconductor device described in claim 5, The first chip mounting portion has a first back surface on which the first semiconductor chip is not placed. The second chip mounting portion has a second back surface on which the second semiconductor chip is not placed. The third chip mounting portion has a third back surface on which the isolator chip is not placed, The first chip resistor is positioned across the first back surface and the third back surface, The second chip resistor is positioned across the second back surface and the third back surface.
In the semiconductor device according to claim 4, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first chip resistor and the second chip resistor is defined as the third direction, the first direction and the third direction are directions that intersect each other.
In the semiconductor device described in claim 8, The first chip mounting portion has a first surface on which the first semiconductor chip is placed, The second chip mounting portion has a second surface on which the second semiconductor chip is arranged. The third chip mounting portion has a third surface on which the isolator chip is arranged. The first chip resistor is arranged across the first surface and the third surface, The second chip resistor is arranged across the second surface and the third surface.
In the semiconductor device described in claim 8, The first chip mounting portion has a first back surface on which the first semiconductor chip is not placed. The second chip mounting portion has a second back surface on which the second semiconductor chip is not placed. The third chip mounting portion has a third back surface on which the isolator chip is not placed, The first chip resistor is positioned across the first back surface and the third back surface, The second chip resistor is positioned across the second back surface and the third back surface.
In the semiconductor device according to claim 4, The resistance value of the first chip resistor is 5 MΩ to 50 MΩ. The resistance value of the second chip resistor is 5 MΩ to 50 MΩ.
In the semiconductor device described in claim 1, The third potential applied to the third chip mounting portion is higher than the first potential and lower than the second potential.
In the semiconductor device described in claim 1, The distance between the lower conductor portion and the first upper conductor portion is defined as the first distance. The distance between the lower conductor portion and the second upper conductor portion is defined as the second distance. When the distance between the lower conductor portion and the third chip mounting portion is defined as the third distance, The third distance is smaller than the first distance. The third distance is smaller than the second distance.
In the semiconductor device described in claim 1, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first upper conductor portion and the second upper conductor portion is defined as the fourth direction, the first direction and the fourth direction are directions that intersect each other.
(a) A step of preparing a lead frame having a first chip mounting section, a second chip mounting section and a third chip mounting section, (b) A step of placing the first semiconductor chip on the first chip mounting portion via a first adhesive, (c) A step of placing a second semiconductor chip on the second chip mounting portion via a second adhesive, (d) A step of placing an isolator chip on the third chip mounting portion via a third adhesive, (e) A step of arranging the first chip resistor via a fourth adhesive so as to span the first chip mounting portion and the third chip mounting portion, (f) A step of arranging a second chip resistor via a fifth adhesive so as to span the second chip mounting portion and the third chip mounting portion, (g) After performing steps (b) through (e), the lead frame is subjected to a heat treatment to cure the first adhesive, the second adhesive, the third adhesive, the fourth adhesive and the fifth adhesive. A method for manufacturing a semiconductor device, comprising:
In the method for manufacturing a semiconductor device according to claim 15, (h) After step (g), the process includes a step of forming a encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor, The aforementioned (h) step is, (h1) A step of sandwiching the lead frame between an upper mold and a lower mold while forming the cavity such that the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged in the cavity. (h2) A step of injecting resin material into the cavity from the gate, Includes, The gate is formed in the upper or lower mold such that the resin material is injected into the narrowest gap in the cavity where the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged.
(a) A step of preparing a lead frame having a first chip mounting section, a second chip mounting section and a third chip mounting section, (b) A step of placing the first semiconductor chip on the first chip mounting portion via a first adhesive, (c) A step of placing a second semiconductor chip on the second chip mounting portion via a second adhesive, (d) A step of placing an isolator chip on the third chip mounting portion via a third adhesive, (e) After performing steps (b) through (d), a first heat treatment is applied to the lead frame to cure the first adhesive, the second adhesive and the third adhesive. (f) After step (e), the first semiconductor chip and the third semiconductor chip are electrically connected to each other with a first bonding wire, and the second semiconductor chip and the third semiconductor chip are electrically connected to each other with a second bonding wire. (g) After step (f), a step of arranging the first chip resistor via a fourth adhesive so as to span the first chip mounting portion and the third chip mounting portion, (h) A step of arranging the second chip resistor via a fifth adhesive so as to span the second chip mounting portion and the third chip mounting portion, (i) After performing steps (g) through (h), a second heat treatment is applied to the lead frame to cure the fourth adhesive and the fifth adhesive. A method for manufacturing a semiconductor device, comprising:
In the method for manufacturing a semiconductor device according to claim 17, (j) After step (i), the process includes a step of forming a encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor, The above step (j) is, (j1) A step of sandwiching the lead frame between an upper mold and a lower mold while forming the cavity such that the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged in the cavity. (j2) A step of injecting resin material into the cavity from the gate, Includes, The gate is formed in the upper or lower mold such that the resin material is injected into the narrowest gap in the cavity where the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged.

Description

This disclosure relates to semiconductor devices and methods for manufacturing the same, and more particularly to techniques applicable to semiconductor devices and methods for manufacturing the same that enable signal transmission between different potentials. Japanese Patent Publication No. 2024-072440 (Patent Document 1) and Japanese Patent Publication No. 2023-181601 (Patent Document 2) describe a transformer technology that enables contactless signal transmission using inductively coupled lower and upper inductors. Japanese Patent Publication No. 2010-016142 (Patent Document 3) describes a technology relating to the structure of a transformer capable of dividing the dielectric strength. Japanese Patent Publication No. 2024-072440Japanese Patent Publication No. 2023-181601Japanese Patent Publication No. 2010-016142 This figure shows an example configuration of a drive control unit that drives a load circuit.This is an explanatory diagram showing an example of signal transmission.This diagram shows a three-chip configuration.This diagram illustrates areas for improvement.This is a diagram explaining the basic concept.This figure shows an example of a transformer layout configuration.This figure shows another example of a transformer layout configuration.This is a top view showing the mounting configuration of a semiconductor device.This is a cross-sectional view along line A-A in Figure 8A.This is a cross-sectional view along the line B-B in Figure 8A.This figure shows an example of the manufacturing process for a semiconductor device in Embodiment 1.This figure shows an example of the manufacturing process for a semiconductor device, following Figure 9.This figure shows an example of the manufacturing process for a semiconductor device, following Figure 10.This figure shows an example of the manufacturing process for a semiconductor device, following Figure 11.This figure shows an example of the manufacturing process for a semiconductor device, following Figure 12.This figure shows an example of the manufacturing process for semiconductor devices, following Figure 13.This figure shows another example of the semiconductor device manufacturing process in Embodiment 1.This figure shows another example of the semiconductor device manufacturing process, following Figure 15.This diagram schematically illustrates the "through-gate molding method."This diagram shows the molding process in Embodiment 1.This figure shows the molding process that follows Figure 18.This figure shows the molding process that follows Figure 19.This figure shows the molding process following Figure 20.This is a top view showing the mounting configuration of a semiconductor device.This is a cross-sectional view along line A-A in Figure 22A.This is a top view showing the mounting configuration of a semiconductor device.This is a cross-sectional view along line A-A in Figure 23A.This is a top view showing the mounting configuration of a semiconductor device.This is a cross-sectional view along line A-A in Figure 24A. In all the drawings illustrating the embodiments, the same reference numerals are generally used for identical components, and repeated explanations are omitted. Hatching may be used even in plan views to improve clarity. The term "digital isolator" is used to broadly encompass devices that enable contactless signal transmission from one circuit to another. For example, digital isolators include transformers utilizing magnetic coupling and capacitors utilizing capacitive coupling. The technical concepts of this disclosure are broadly applicable to digital isolators, including transformers and capacitors. The following explanation will focus on transformers. Furthermore, a chip with a "digital isolator" formed on it is called an "isolator chip." Similarly, a chip with a "transformer" formed on it is called a "transformer chip." Therefore, "isolator chip" is a broader term encompassing "transformer chip." <Circuit Configuration> Figure 1 shows an example of the configuration of a drive control unit that drives a load circuit such as a motor. As shown in Figure 1, the drive control unit includes a control circuit CC, a transmitting circuit TX1, a receiving circuit RX1, a transmitting circuit TX2, a receiving circuit RX2, transformers TR1 and TR2, a drive circuit DR, and an inverter INV. The transmitting circuit TX1 and the receiving circuit RX1 are circuits for transmitting control signals output from the control circuit CC to the drive circuit DR. On the other hand, the transmitting circuit TX2 and the receiving circuit RX2 are circuits for transmitting signals output from the drive circuit DR to the control circuit CC. The control circuit CC is a circuit that controls the drive circuit DR. The drive circuit DR is a circuit that operates the inverter INV, which controls the load circuit LOD, based on the control from the control circuit CC. The inverter INV is electrically connected to the load circuit LOD. The control circuit