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JP-2026076040-A - Synchronization circuit, modulator, transmitter, synchronization control method, and program

JP2026076040AJP 2026076040 AJP2026076040 AJP 2026076040AJP-2026076040-A

Abstract

[Challenge] To recover from a clock interruption while suppressing shocks. [Solution] According to the embodiment, the synchronization circuit comprises an oscillator, a first frequency divider, a second frequency divider, a first comparator, a frequency multiplier, a third frequency divider, a second comparator, and a third comparator. The first frequency divider divides the reference clock signal to generate a first frame pulse. The second frequency divider divides the local signal of the oscillator to generate a second frame pulse. The first comparator feedback-controls the frequency of the local signal according to the phase difference between the first frame pulse and the second frame pulse. The frequency multiplier multiplies the local signal to generate a pulse signal. The third frequency divider divides the pulse signal to generate an internal clock. The second comparator switches the division ratio of the second frequency divider according to the phase difference between the system switching synchronization signal and the internal clock. The third comparator switches the division ratio of the third frequency divider according to the phase difference between the system switching synchronization signal and the internal clock. [Selection Diagram] Figure 4

Inventors

  • 村上 泰樹

Assignees

  • 株式会社東芝

Dates

Publication Date
20260511
Application Date
20241023

Claims (11)

  1. In a synchronization circuit applicable to a modulator that receives a broadcast TS (Transport Stream) signal, a reference clock signal, and a system switching synchronization signal as inputs and outputs a digitally modulated signal, An oscillator that generates a local signal, A first frequency divider that divides the reference clock signal to generate a first frame pulse, A second frequency divider that divides the local signal with a switchable frequency division ratio to generate a second frame pulse, A first comparator controls the oscillator according to the phase difference between the first frame pulse and the second frame pulse to feedback control the frequency of the local signal, A frequency multiplier that multiplies the aforementioned local signal to generate a pulse signal, A third frequency divider that divides the pulse signal with a switchable frequency division ratio to generate an internal clock, A second comparator controls the frequency division ratio of the second frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock, A synchronization circuit comprising a third comparator that switches and controls the frequency division ratio of the third frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock.
  2. Furthermore, the synchronization circuit according to claim 1 comprises a counter that counts up the pulses of the generated internal clock up to a specified value and inputs it to the second comparator.
  3. The synchronization circuit according to claim 1, wherein the third frequency divider generates an internally generated clock synchronized with a 512/63 [MHz] reference clock signal.
  4. The first frequency divider is a 17-frequency divider that divides a 512/63 [MHz] reference clock signal by 17. The second frequency divider is a 14-frequency divider that divides the local signal by 14. The aforementioned multiplier is a 17-multiplier that multiplies the local signal by 17 times. The synchronization circuit according to claim 1, wherein the third frequency divider is a 14-frequency divider that divides the pulse signal by 14.
  5. The synchronization circuit according to claim 4, wherein the second frequency divider switches the division ratio to 13 when the phase of the system switching synchronization signal leads the phase of the generated internal clock, and switches the division ratio to 15 when the phase of the system switching synchronization signal lags behind the phase of the generated internal clock.
  6. The first frequency divider is a 17-frequency divider that divides a 512/63 [MHz] reference clock signal by 17. The second frequency divider is a 14-frequency divider that divides the local signal by 14. The aforementioned multiplier is a 17-multiplier that multiplies the local signal by 17 times. The synchronization circuit according to claim 2, wherein the third frequency divider is a 14-frequency divider that divides the pulse signal by 14.
  7. The synchronization circuit according to claim 4, wherein the second frequency divider switches the division ratio to 13 when the phase of the system switching synchronization signal leads the phase of the generated internal clock, and switches the division ratio to 15 when the phase of the system switching synchronization signal lags behind the phase of the generated internal clock.
  8. A modulator comprising a synchronization circuit according to any one of claims 1 to 7, which digitally modulates the broadcast TS signal based on the reference clock signal and outputs a digitally modulated signal.
  9. The modulator described in claim 8 is provided as the primary system and the backup system, A transmitting device comprising redundant switching means for switching between the modulator of the active system and the modulator of the backup system at the timing of the system switching synchronization signal.
  10. In a synchronization control method in which a synchronization circuit comprising an interface section that receives a reference clock signal and a system switching synchronization signal, and an oscillator that generates a local signal, is controlled by a processor, The process by which the processor compares the phase of the system switching synchronization signal with the phase of the MSB (Most Significant Bit) of the count-up value of the generated internal clock generated from the local signal, A synchronization control method comprising the process of the processor comparing the phase of the system switching synchronization signal with the phase of the generated internal clock after a predetermined time has elapsed since the comparison result between the phase of the system switching synchronization signal and the phase of the MSB stabilizes, and repeating the frequency of the oscillator's local signal at predetermined intervals based on the result.
  11. A program stored in the memory of an embedded computer comprising memory and a processor, which causes the processor to execute the synchronization control method described in claim 10.

Description

Embodiments of this invention relate to a synchronization circuit, a modulator, a transmitting device, a synchronization control method, and a program. Television and radio broadcasting infrastructure utilizes STL/TTL (Studio to Transmitter Lync / Transmitter to Transmitter Lync) equipment to transmit broadcast material from studios to main transmission stations, or from main transmission stations to relay transmission stations. STL/TTL systems can be connected in a daisy-chain fashion (STL → TTL → TTL →…) to transmit signals over long distances. The devices are connected via high-frequency wireless communication (digital microwave) or fiber optic communication interfaces. The STL (Speaker Transmission Line) system is equipped with a modulator (64QAM MOD) that modulates the TS (Transport Stream) signal, which is the broadcast material, using 64QAM (Quadrature Amplitude Modulation). The modulator receives the TS signal, an 8M CLK signal, and an Fsync signal from the master system. It digitally modulates the TS signal using 64QAM and outputs a 130MHz IF (Intermediate Frequency) signal (digitally modulated signal). Here, the Fsync signal is a system switching synchronization signal used to synchronize the switching between the active and backup systems within the system. Japanese Patent Publication No. 2019-50505 Figure 1 is a system diagram showing an example of a broadcasting system according to the embodiment.Figure 2 is a block diagram showing an example of a transmitting device installed at the main station transmitting station 60.Figure 3 is a block diagram showing an example of a receiving device installed at the relay transmission station 70.Figure 4 is a block diagram showing an example of a synchronization circuit provided in the modulators 11 and 12 shown in Figure 2.Figure 5 is a timing chart illustrating the state of each signal after the input 8M CLK has been restored from an interruption.Figure 6 is a timing chart illustrating the behavior of comparator 10 when a Stable input is received.Figure 7 is a functional block diagram showing another example of a synchronous circuit.Figure 8 is a flowchart showing an example of the processing procedure of the processor 34. Figure 1 is a system diagram showing an example of a terrestrial digital broadcasting system according to the embodiment. Terrestrial digital broadcasting programs are transmitted using various relay methods. For example, there are broadcast wave relay methods that directly receive and relay broadcast waves from higher-level transmission stations, and TTL (Transmitter to Transmitter Link) relay methods that use microwave band radio frequencies as a medium for relaying. TTL relay systems are broadly classified into TS (Transport Stream) transmission systems and IF (Intermediate Frequency) transmission systems. The TS transmission system is a digital regenerative relay system that transmits the TS signal as a 64QAM (Quaternary Amplitude Modulation) signal, and the receiving end regenerates the TS signal. The IF transmission system transmits the OFDM (Quaternary Frequency Division Multiplexing) signal, which is a broadcast wave, at microwave frequencies and is a non-regenerative relay system. In Figure 1, broadcasting station 50 transmits a broadcast TS signal to the master transmission station 60. The master transmission station 60 transmits the broadcast TS signal from broadcasting station 50 to the relay transmission station 70 using the TS transmission method. At both ends of the TS transmission section, the master transmission station 60 is equipped with transmitting equipment, and the relay transmission station 70 is equipped with receiving equipment. Figure 2 is a block diagram showing an example of a transmitting device installed at the master station 60. The transmitting device 100 in Figure 2 includes two modulators 11 and 12. Modulator 11 functions as the master (active/No. 1) system, and modulator 12 functions as the slave (backup/No. 2) system. Both modulators 11 and 12 receive inputs for the TS signal, the 8M CLK signal, and the Fsync signal. Under the control of the modulator control unit 13, modulators 11 and 12 each modulate the TS signal using 64QAM and output an IF signal. The transmitting device also includes a redundant switching mechanism that switches between the active modulator 11 and the backup modulator 12 at the timing of the Fsync signal, which is a system switching synchronization signal. The IF signal from modulator 11 is input to the transmitter converter 14, upconverted, and converted into an RF (Radio Frequency) signal within the transmission bandwidth. Similarly, the IF signal from modulator 12 is converted into an RF signal by the transmitter converter 15. Here, the transmitter converter 14 is the master system, and the transmitter converter 15 is the slave system. Transmitters 14 and 15 are controlled by the transmitter converter control unit 16. The RF signals from the transmitter converters 14 and 15