JP-2026076115-A - Electronic device having transistors stacked vertically on a substrate

Abstract

[Problem] To provide an electronic device that increases performance, reliability, and IC device density. [Solution] In an integrated circuit (IC), the gate structure 151 includes a first surface facing a second surface. A first semiconductor layer 144 is arranged between the first surface of the gate structure and the lower dielectric structure 126. A second semiconductor layer 146 is located on the second surface of the gate structure. In an electronic device including first and second gate electrodes 136 within a dielectric layer 150 on a substrate, the first and second gate electrodes overlap one or more conductive wiring structures. A gate dielectric layer 148 overlaps the first and second gate electrodes. A first semiconductor layer is arranged on a gate dielectric layer above the first gate electrode, and a second semiconductor layer is arranged on a gate dielectric layer above the second gate electrode. A first source/drain structure pair 132, 134 is arranged on the first semiconductor layer, and a second source/drain structure pair 140, 142 is arranged on the second semiconductor layer. [Selection Diagram] Figure 1

Inventors

• ▲蒋▼ 國璋
• 張 志宇
• 施 ▲ユー▼全
• 陳 晏誼
• 王 冠奇

Assignees

• 台湾積體電路製造股▲ふん▼有限公司

Dates

Publication Date

20260511

Application Date

20251002

Priority Date

20241023

Claims (20)

1. A lower dielectric structure superimposed on a semiconductor substrate, A gate structure on the lower dielectric structure, The gate structure includes a first surface facing a second surface, A first semiconductor layer arranged between the first surface of the gate structure and the lower dielectric structure, A second semiconductor layer on the second surface of the gate structure, An integrated chip equipped with these features.
2. The integrated chip according to claim 1, further comprising a plurality of conductive wires and a plurality of conductive vias disposed within the lower dielectric structure and located below the first semiconductor layer and the second semiconductor layer.
3. The gate structure includes a gate electrode, a first gate dielectric layer, and a second gate dielectric layer. The first gate dielectric layer is arranged between the gate electrode and the first semiconductor layer. The second gate dielectric layer is arranged between the gate electrode and the second semiconductor layer. The integrated chip according to claim 1.
4. A first source/drain structure pair arranged on the first semiconductor layer and spaced apart on the opposite side of the gate electrode, A second source/drain structure pair arranged on the second semiconductor layer and spaced apart on the opposing side of the gate electrode, The integrated chip according to claim 3, comprising:
5. The integrated chip according to claim 4, further comprising conductive vias extending vertically from the first source/drain structure in the first source/drain structure pair to the first source/drain structure in the second source/drain structure pair.
6. The conductive vias are in direct contact with the opposing side walls of the first semiconductor layer and the opposing side walls of the second semiconductor layer. The integrated chip according to claim 5.
7. The outer wall of the first semiconductor layer is positioned with a gap between the first source/drain structure pair, The outer wall of the second semiconductor layer is positioned with a gap between the second source/drain structure pair. The integrated chip according to claim 4.
8. The first semiconductor layer comprises a first material, the second semiconductor layer comprises a second material, and the semiconductor substrate comprises a third material. The first material, the second material, and the third material are different from each other. The integrated chip according to claim 1.
9. The underlying wiring structure on the semiconductor substrate, A first semiconductor device on the lower wiring structure, The first semiconductor device includes a first source/drain structure pair on the lower wiring structure, a first semiconductor layer on the first source/drain structure pair, and a first gate dielectric layer on the first semiconductor layer. The gate electrode on the first gate dielectric layer, A second semiconductor device on the first semiconductor device, The second semiconductor device includes a second gate dielectric layer on the gate electrode, a second semiconductor layer on the second gate dielectric layer, and a second source/drain structure pair on the second semiconductor layer, An integrated chip equipped with these features.
10. The first dielectric layer is further disposed between the first gate dielectric layer and the second gate dielectric layer, The first dielectric layer encloses the gate electrode from the side. The integrated chip according to claim 9.
11. The first semiconductor device is configured as a p-channel transistor, The second semiconductor device is configured as an n-channel transistor. The integrated chip according to claim 9.
12. The outer wall of the first semiconductor layer is positioned with a gap between the first source/drain structure pair, The outer wall of the second semiconductor layer is positioned with a gap between the second source/drain structure pair. The integrated chip according to claim 9.
13. The first gate dielectric layer is in direct contact with the opposing sidewall of the first semiconductor layer. The integrated chip according to claim 12.
14. The first semiconductor layer comprises a first metal oxide, The second semiconductor layer contains a second metal oxide different from the first metal oxide. The integrated chip according to claim 9.
15. The semiconductor substrate further comprises transistors arranged on the semiconductor substrate, The aforementioned transistor is A source/drain region pair arranged within the semiconductor substrate, Includes a lower gate electrode on the semiconductor substrate between the source/drain region pair, Each individual source/drain region in the source/drain region pair is electrically coupled to the first source/drain structure in the first source/drain structure pair via the lower wiring structure. The integrated chip according to claim 9.
16. A method for forming an integrated chip, Forming a sub-wiring structure on a semiconductor substrate, Forming a first source/drain structure pair on the lower wiring structure, The first semiconductor layer is deposited on the first source/drain structure pair, The first gate dielectric layer is deposited on the first semiconductor layer, Forming a gate electrode on the first gate dielectric layer, Forming a second gate dielectric layer on the gate electrode, Forming a second semiconductor layer on the second gate dielectric layer, Forming a second source/drain structure pair on the second semiconductor layer, Methods that include...
17. The method according to claim 16, further comprising forming a conductive via between the first source/drain structure in the first source/drain structure pair and the second source/drain structure in the second source/drain structure pair.
18. The conductive via and the second source/drain structure are formed simultaneously. The method according to claim 17.
19. Forming the aforementioned terminal Depositing a dielectric layer on the aforementioned first gate dielectric layer, Etching the dielectric layer to form an opening within the dielectric layer, Depositing one or more conductive materials within the opening, Performing a planarization process on one or more conductive materials, The method according to claim 17, including the method described in claim 17.
20. Depositing one or more conductive materials is Depositing a liner layer within the aforementioned opening, Depositing a conductive core on the liner layer, The method according to claim 19, including the method described in claim 19.

Description

The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As ICs evolve, the size of semiconductor devices (e.g., transistor area) is scaled down, for example, by reducing the minimum feature size and/or the lateral spacing between adjacent semiconductor devices. This has led to an increase in device density (e.g., the number of semiconductor devices integrated into a given area). However, as lateral spacing between adjacent semiconductor devices continues to shrink, increasing device density without negatively impacting semiconductor device performance is becoming increasingly difficult. Therefore, advancements in the IC manufacturing industry that increase device density without negatively affecting semiconductor device performance are highly desirable. The aspects of this invention will be best understood from the following detailed description, in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity in the description. The images show cross-sectional views of several embodiments of an integrated circuit (IC) having electronic devices, including transistors stacked perpendicularly to each other on a semiconductor substrate.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The following are cross-sectional views of several other embodiments of the IC shown in Figure 1.The diagram shows cross-sectional views of several embodiments of an IC having an electronic device including transistors that are stacked perpendicularly to each other in a first region of a semiconductor substrate and are adjacent laterally to each other in a second region of the semiconductor substrate.Another cross-sectional view of several embodiments of an IC having an electronic device including transistors stacked perpendicularly to each other in a first region of a semiconductor substrate and adjacent laterally to each other in a second region of the semiconductor substrate.The layout diagrams of several embodiments of the IC in Figure 5A are shown, cut along the line A-A' in Figure 5A.Another layout diagram of several embodiments of the IC in Figure 5A, cut along the line A-A' in Figure 5A, is shown.The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The images show cross-sectional views in various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular to each other.The following are cross-sectional views of various cross-sectional views of several embodiments of a first method for forming an IC having an electronic device including transistors stacked perpendicular