JP-2026076182-A - Systems and methods for coupling between qubits

Abstract

[Problem] Solve the connectivity problem between qubits. [Solution] The superconducting integrated circuit includes a first superconducting device 102 having a first superconducting loop 108 with a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device 104 having a second superconducting loop 112 with a second superconducting trace in a second layer. The first superconducting loop intersects with the second superconducting loop in an intersection region 120. At least a portion of each of the first and second superconducting traces inside the intersection region follows a detour path that is narrower than at least a portion of each of the traces outside the intersection region and inductively approaches at least a portion of the other path. [Selection Diagram] Figure 1

Inventors

• モウラヴィー，レーザ
• ブースビー，ケリー ティー．アール．
• フォルクマン，マーク エイチ．
• ブニク，ポール アイ．

Assignees

• ディー－ウェイブ システムズ インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20251226

Priority Date

20200630

Claims (20)

1. A first superconducting device comprising a first superconducting loop including a first superconducting trace in a first layer of a superconducting integrated circuit, A second superconducting device comprising a second superconducting loop including a second superconducting trace in a second layer of the superconducting integrated circuit, wherein the second layer lies on and/or adjacent to the first layer, and the second layer is separated from the first layer by an intervening layer, A superconducting integrated circuit comprising an intersection region in which the first superconducting loop intersects the second superconducting loop by projection, wherein at least a portion of the first superconducting trace inside the intersection region is narrower than at least a portion of the first superconducting trace outside the intersection region, at least a portion of the second superconducting trace inside the intersection region is narrower than at least a portion of the second superconducting trace outside the intersection region, at least a portion of the first superconducting trace inside the intersection region follows a first detour path, at least a portion of the second superconducting trace inside the intersection region follows a second detour path, and the first detour path and the second detour path are inductively close to each other with respect to at least a portion of the length of the first detour path.
2. The superconducting integrated circuit according to claim 1, wherein the first detour path and the second detour path lie at least partially over each other with respect to at least a portion of the length of the first detour path.
3. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting loop intersects substantially perpendicularly with the second superconducting loop.
4. The superconducting integrated circuit according to claim 1 or 2, wherein each of the first superconducting trace and the second superconducting trace comprises a superconducting metal.
5. The superconducting integrated circuit according to claim 4, wherein each of the superconducting metals includes a superconducting metal selected from the group consisting of niobium and aluminum.
6. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting device further includes a first Josephson junction, the first Josephson junction blocking the first superconducting loop, and the second superconducting device further includes a second Josephson junction, the second Josephson junction blocking the second superconducting loop.
7. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting device is a first superconducting flux qubit, and the second superconducting device is a second superconducting flux qubit.
8. The superconducting integrated circuit according to claim 1 or 2, wherein at least a portion of the first superconducting trace inside the intersection region includes four direction changes.
9. The superconducting integrated circuit according to claim 1 or 2, wherein the first shape of the first bypass path matches the second shape of the second bypass path.
10. The superconducting integrated circuit according to claim 1 or 2, wherein the intervening layer includes an insulating layer.
11. The superconducting integrated circuit according to claim 10, wherein the insulating layer includes a dielectric material and/or an air bridge.
12. The superconducting integrated circuit according to claim 11, wherein the dielectric material comprises at least one of silicon dioxide or silicon nitride.
13. The superconducting integrated circuit according to claim 1 or 2, further comprising a coupling device coupled to the first superconducting device and the second superconducting device, and connected in a manner that enables communication between the first superconducting device and the second superconducting device to provide mediating coupling.
14. The superconducting integrated circuit according to claim 1 or 2, wherein each of the at least portion of the first superconducting trace inside the intersection region and each of the at least portion of the second superconducting trace inside the intersection region includes one or more U-shaped contours.
15. A quantum computer comprising a superconducting integrated circuit according to any one of claims 1 to 14.
16. A method for synchronizing the magnitude of a connectable coupling between a first superconducting device and a second superconducting device, wherein the magnitude of the connectable coupling is the sum of the magnitudes of the mediating connectable coupling and the direct connectable coupling. To determine the target size of the communicable coupling between the first and second superconducting devices, Determining the difference between the size of the mediating connectable coupling and the size of the target, Determining the adjustment tolerance based at least partially on the difference between the size of the mediating coupling and the size of the target, The first superconducting loop of the first superconducting device is attached to the first layer, The second superconducting loop of the second superconducting device is attached to the second layer, wherein the second superconducting loop intersects with the first superconducting loop to form an intersection region. By following the first detour path, at least a portion of the first superconducting loop inside the intersection region is adjusted by the adjustment tolerance range such that it becomes narrower outside the intersection region than at least a portion of the first superconducting loop, A method comprising following a second detour path and adjusting at least a portion of the second superconducting loop within the intersection region by the adjustment tolerance range such that it is narrower outside the intersection region than at least a portion of the second superconducting loop, wherein the first detour path and the second detour path are inductively close to each other with respect to at least a portion of the length of the first detour path.
17. The method according to claim 16, further comprising attaching an intervening layer between the first layer and the second layer.
18. The method according to claim 17, wherein the attachment of an intervening layer between the first layer and the second layer includes attaching an insulating layer.
19. The method according to claim 18, wherein the deposition of an insulating layer includes deposition of a dielectric material layer and/or the formation of an air bridge.
20. The method according to any one of claims 16 to 19, wherein attaching the second superconducting loop of the second superconducting device to the second layer includes attaching the second superconducting loop of the second superconducting device to the second layer such that at least a portion of the second layer lies on top of at least a portion of the first layer.

Description

Background: This disclosure generally relates to improving the performance of quantum processors, and in particular to coupling between qubits in superconducting quantum processors. Quantum devices are structures that can observe quantum mechanical effects. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics, which use electron spin as a resource, and superconducting circuits. Both spin and superconductivity are examples of quantum mechanical phenomena. Quantum devices can be used, for example, in instruments and computing systems. Quantum computing and quantum information processing encompass several types of marketable products. A quantum computer is a system that performs calculations on data by directly using quantum mechanical phenomena (e.g., superposition, tunneling, and quantum entanglement). Data can be represented in a quantum computer using quantum binary numbers (also referred to as qubits in this application). Quantum computers can provide exponential speedups to certain types of computational problems (e.g., quantum physics simulations). Favorable speedups may exist for other types of problems as well. In some implementations, quantum computers include quantum circuit models. In other implementations, quantum computers include adiabatic quantum computers. Adiabatic quantum computers can be useful, for example, for solving NP-hard optimization problems. Adiabatic Quantum Computation Adiabatic quantum computation typically involves evolving a system from a known initial Hamiltonian (the Hamiltonian is an operator whose eigenvalues are the allowable energy of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of adiabatic evolution is linear interpolation between the initial and final Hamiltonians. An example is given below. H e = (1-s) H i +sH f However, Hi is the initial Hamiltonian, H f is the final Hamiltonian, He is the evolutionary or instantaneous Hamiltonian, and s is the evolutionary coefficient that controls the rate of evolution. As the system evolves, the evolutionary coefficient s transitions from 0 to 1, initially (s=0) when the evolutionary Hamiltonian He is equal to the initial Hamiltonian Hi , and finally (s=1) when the evolutionary Hamiltonian He is equal to the final Hamiltonian H f . Before evolution begins, the system is typically initialized to the ground state of the initial Hamiltonian H i , and the goal is to evolve the system in a way that leads to the ground state of the final Hamiltonian H f . If the evolution is too rapid, the system may be excited to a higher energy state (e.g., the first excited state). In this application, adiabatic evolution is defined as evolution that satisfies the adiabatic conditions expressed below. however, is the time derivative of s, g(s) is the energy difference between the ground state and the first excited state of the system (also called the gap size in this application) as a function of s, and δ is a coefficient much smaller than 1 (δ << 1). Generally, the initial Hamiltonian H i and the final Hamiltonian H f are inexchangeable, i.e., [H i , H f ] ≠ 0. The process of changing the Hamiltonian in adiabatic quantum computing is referred to in this application as evolution. The rate of change of the evolution coefficient s is preferably slow enough to keep the system in the ground state of the evolved Hamiltonian He during evolution and to avoid transitions in anticrossing (when the gap size is minimal). The evolution schedule may be linear, nonlinear, parametric, etc. Further details relating to adiabatic quantum computing systems, methods, and apparatus are described, for example, in U.S. Patents 7,135,701 and 7,418,283. Quantum Annealing is a computational method that can be used to find the low-energy state of a system, typically and preferably the ground state of the system. Similar in concept to classical annealing, quantum annealing relies on the fundamental principle that natural systems tend to be in lower-energy states because lower-energy states are more stable. While classical annealing uses classical thermal fluctuations to guide the system to a low-energy state (ideally, the global energy minimum), quantum annealing can reach the global energy minimum more accurately and/or quickly than classical annealing by using quantum effects (e.g., quantum tunneling). In quantum annealing, thermal effects and other noise may be present to aid the annealing process. The final low-energy state may not be the global energy minimum. Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally remains in its ground state from the start through its entire adiabatic evolution. Those skilled in the art will generally see that quantum annealing systems and methods can be implemented on adiabatic quantum computers. Throughout this specification and t