JP-2026076230-A - Image sensor and imaging device

JP2026076230AJP 2026076230 AJP2026076230 AJP 2026076230AJP-2026076230-A

Abstract

[Problem] To suppress the superposition of noise on the pixel signal caused by increases and decreases in charge during charge transfer in the image sensor. [Solution] An image sensor comprising a first semiconductor chip having a first block, a second block, and a third block, and a second semiconductor chip having a first circuit section, a second circuit section, and a third circuit section, wherein the first circuit section is positioned to overlap with the first block in the stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked, the second circuit section is positioned to overlap with the second block in the stacking direction, and the third circuit section is positioned to overlap with the third block in the stacking direction. [Selection Diagram] Figure 4

Inventors

栗山孝司

Assignees

株式会社ニコン

Dates

Publication Date: 20260511
Application Date: 20260120

Claims (1)

A first block having a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and a third photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit, a block arranged in the column direction alongside the first block having a fourth photoelectric conversion unit that converts light into electric charge, a fifth photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the fourth photoelectric conversion unit, and A first semiconductor chip comprising: a second block having a photoelectric conversion unit for conversion, a sixth photoelectric conversion unit arranged in the row direction alongside the fourth photoelectric conversion unit; a third block arranged in the row direction alongside the first block, having a seventh photoelectric conversion unit for converting light into electric charge; an eighth photoelectric conversion unit for converting light into electric charge, arranged in the column direction alongside the seventh photoelectric conversion unit; and a ninth photoelectric conversion unit for converting light into electric charge, arranged in the row direction alongside the seventh photoelectric conversion unit; A semiconductor chip stacked with the first semiconductor chip, comprising: a first circuit section including a first signal processing unit that performs signal processing on a first signal based on a charge converted by the first photoelectric conversion unit and a second signal based on a charge converted by the second photoelectric conversion unit and a second signal processing unit that performs signal processing on a third signal based on a charge converted by the third photoelectric conversion unit; a second circuit section including a third signal processing unit that performs signal processing on a fourth signal based on a charge converted by the fourth photoelectric conversion unit and a fifth signal based on a charge converted by the fifth photoelectric conversion unit and a fourth signal processing unit that performs signal processing on a sixth signal based on a charge converted by the sixth photoelectric conversion unit; a third circuit section including a fifth signal processing unit that performs signal processing on a seventh signal based on a charge converted by the seventh photoelectric conversion unit and an eighth signal based on a charge converted by the eighth photoelectric conversion unit and a sixth signal processing unit that performs signal processing on a ninth signal based on a charge converted by the ninth photoelectric conversion unit, The first circuit section is positioned in a location that overlaps with the first block in the stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked. The second circuit section is positioned in a location that overlaps with the second block in the stacking direction. The third circuit section is an image sensor positioned to overlap with the third block in the stacking direction.

Description

This invention relates to an image sensor and an imaging device. In some image sensors where pixels are arranged in a matrix, a global shutter is electronically realized by simultaneously transferring electric charge using a memory circuit consisting of transistors and storage capacitors (see, for example, Patent Document 1). Patent Document 1: Japanese Unexamined Patent Publication No. 2011-119950 This is a cross-sectional view of a back-illuminated image sensor according to this embodiment.This diagram illustrates the pixel arrangement and unit blocks of the imaging chip.This is a circuit diagram corresponding to a pixel.This shows a schematic representation of the unit block, its surrounding circuits, and their connection relationships.This shows a general overview of the connections between peripheral circuits and other components.This is a block diagram showing the configuration of the imaging device according to this embodiment.This is a block diagram showing the specific configuration of the drive unit.This chart shows the timing of operations such as charge accumulation and transfer in pixels.This shows the timing chart for the operation of reading out the pixel signal from each pixel.This is a timing chart showing the readout timing of multiple pixels included in the imaging unit.Another example of the connection relationships of peripheral circuits, etc., is shown. The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. Figure 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 comprises an imaging chip 113 that outputs pixel signals corresponding to incident light, a signal processing chip 111 that processes the pixel signals, and a memory chip 112 that stores the pixel signals. These imaging chip 113, signal processing chip 111, and memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like. As shown in the figure, the incident light primarily enters in the Z-axis positive direction, indicated by the white arrow. In this embodiment, the side of the imaging chip 113 that receives the incident light is referred to as the back surface. Furthermore, as shown in the coordinate axes, the direction to the right of the paper, perpendicular to the Z-axis, is defined as the X-axis positive direction, and the direction towards the viewer, perpendicular to both the Z-axis and X-axis, is defined as the Y-axis positive direction. In the following figures, the coordinate axes are displayed using the coordinate axes of Figure 1 as a reference, so that the orientation of each figure is clear. An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is located on the back side of the wiring layer 108. The PD layer 106 has a plurality of two-dimensionally arranged PDs (photodiodes) 104, and transistors 105 provided corresponding to the PDs 104. A color filter 102 is provided on the incident light side of the PD layer 106 via a passivation film 103. The color filter 102 has multiple types that transmit different wavelength regions and has a specific arrangement corresponding to each PD 104. The arrangement of the color filter 102 will be described later. A set of color filter 102, PD 104, and transistor 105 forms a single pixel. On the incident light side of the color filter 102, a microlens 101 is provided, corresponding to each pixel. The microlens 101 focuses the incident light toward the corresponding PD 104. The wiring layer 108 has wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayered, and may also contain passive and active elements. Multiple bumps 109 are arranged on the surface of the wiring layer 108. These bumps 109 are aligned with multiple bumps 109 provided on the opposing surface of the signal processing chip 111. When pressure is applied to the imaging chip 113 and the signal processing chip 111, the aligned bumps 109 are joined together and electrically connected. Similarly, multiple bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and when pressure is applied to the signal processing chip 111 and the memory chip 112, the aligned bumps 109 are joined together and electrically connected. Furthermore, the joining of bumps 109 is not limited to Cu bump joining by solid-phase diffusion; microbump joining by solder melting may also be employed. Also, it is sufficient to provide approximately one bump 109 per output wiring, for example, as described later. Therefore, the size of the bumps 109 may be larger than the pitch of the PD 104. Additionally, in the peri