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JP-2026076283-A - Shared multiport memory from a single port

JP2026076283AJP 2026076283 AJP2026076283 AJP 2026076283AJP-2026076283-A

Abstract

[Problem] To provide a multiport memory system that performs multiple read and write operations in parallel, using single-port memory, which is a memory element that can perform read-only or write-only operations at any given time. [Solution] A multiport memory system can perform multiple reads and writes (e.g., 1R/1W, 1R/3W, 2R/2W, 3R/1W, etc.) in parallel, even if the memory within the system can only perform one read or one write at any given time. [Effect] Area and power consumption can be reduced. [Selection Diagram] Figure 1

Inventors

  • バルケ，リチャード・ルイス
  • マクグラス，ジョン・エドワード

Assignees

  • ザイリンクス インコーポレイテッド

Dates

Publication Date
20260511
Application Date
20260204
Priority Date
20210323

Claims (20)

  1. A multi-port memory system, A single-port memory capable of performing only one read or one write operation at a time, wherein the address space of the single-port memory is less than or equal to half the address space of the multi-port memory system, A divider configured to divide the received read address and write address, A first register is connected to the write data port of the single-port memory and configured to store the received write data word when the single-port memory is performing a read operation. The system comprises a second register, which is coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during the read operation, From the perspective of an external entity, the multiport memory system is a multiport memory system that performs at least one of the following: (i) performing at least one read and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel using the single port memory.
  2. The multiport memory system according to claim 1, wherein during a write operation, multiple data words are received at the write data port, and one of the multiple data words includes the write data word stored in the first register during the read operation.
  3. The multiport memory system according to claim 1, wherein the single-port memory stores a plurality of data words in each memory location, each of the plurality of data words corresponds to a different address in the address space of the multiport memory system, but the plurality of data words correspond to the same address in the address space of the single-port memory.
  4. The multiport memory system according to claim 1, further comprising a multiplexer connected to the read data port at a first input and to the output of the second register at a second input, the multiplexer configured to select whether to transmit, as read data, a second data word read from the single-port memory during the read operation, or the first data word previously stored in the second register.
  5. The multiport memory system is configured to start and stop data writing at any cycle using write control and read control, and the multiport memory system is configured A first multiplexer connected between the single-port memory and the received read address signal, wherein the selection signal of the first multiplexer is controlled by the read control, A third register, coupled to the input of the first multiplexer and configured to store the received read address signal, A second multiplexer connected between the write data port and the received write data, wherein the selection signal of the second multiplexer is controlled by the write control, A fourth register, coupled to the input of the second multiplexer and configured to store at least a portion of the received write data, A third multiplexer connected between the read output of the multiport memory system and the read data port, wherein the selection signal of the third multiplexer is controlled by the read control, The multiport memory system according to claim 1, further comprising: a fifth register coupled to the input of the third multiplexer and configured to store at least a portion of the read data provided by the read data port.
  6. The system further comprises a plurality of read buffers coupled to the read data port, each of the plurality of read buffers configured to store a plurality of data words received from the single port memory during its respective read operation, and each of the plurality of read buffers outputs its respective data word during each read and write operation performed by the single port memory. From the aforementioned viewpoint of the external entity, the multiport memory system according to claim 1, wherein the multiport memory system performs a plurality of read operations in parallel.
  7. The single-port memory further comprises a plurality of write buffers coupled to the write data port, each of the plurality of write buffers configured to buffer a plurality of write data words when the single-port memory performs a read operation, and at least one of the plurality of write buffers outputs one of the buffered plurality of write data words to the single-port memory when a write operation is performed. From the aforementioned viewpoint of the external entity, the multiport memory system according to claim 1, wherein the multiport memory system performs a plurality of write operations in parallel.
  8. Multiple read buffers coupled to the aforementioned read data port, The multiport memory system according to claim 1, further comprising a plurality of write buffers coupled to the write data port, wherein the multiport memory system can be configured to function as one of 1R/xW, yR/xW, yR/1W, xW, or yR memory by selectively using a subset of the plurality of read and write buffers, and x and y are integer values of 2 or more.
  9. The multiport memory system according to claim 8, wherein the plurality of read buffers and the plurality of write buffers are dynamically selectable, and as a result, the multiport memory system can switch to perform a different number of reads or writes in parallel from one of the 1R/xW, yR/xW, yR/1W, xW, or yR memory.
  10. The single-port memory stores pulse data for peak cancellation-crest factor reduction (PC-CFR), and the multi-port memory system, The multiport memory system according to claim 1, comprising a plurality of pulse cancellation units coupled to the single-port memory using a port.
  11. A method for performing read and write operations in parallel using single-port memory, During the first cycle, write a first set of data words to the single-port memory using the write data port, During the second cycle, read a second set of data words from the first memory address of the single-port memory using the read data port, During the second cycle, the first data word among the second plurality of data words is stored in the first register coupled to the read data port, During the second cycle, the second data word among the second plurality of data words is output as read data, During the second cycle, the first received word is stored in a second register connected to the write data port of the single-port memory, During the third cycle, the first received word and the second received word are written to the second memory address of the single-port memory using the write data port, A method comprising outputting, during the third cycle, the second data word among the second plurality of data words as read data.
  12. From the perspective of an external entity, the method according to claim 11, wherein the single-port memory is part of a multi-port memory system that performs at least one of the following: (i) performing at least one read operation and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel.
  13. The method according to claim 12, wherein the address space of the single-port memory is less than or equal to half the address space of the multi-port memory system.
  14. The method according to claim 13, further comprising dividing the write and read addresses used to perform read and write operations in the single-port memory by an integer value that is 2 or greater and a power of 2.
  15. The method according to claim 11, wherein the first, second, and third cycles are consecutive cycles.
  16. The method according to claim 11, further comprising adding a delay to the write data port and the read data port of the single-port memory, thereby starting and stopping the write operation at any cycle in the single-port memory.
  17. The received read address is stored in a register, The method according to claim 16, further comprising selecting at least one of the received read address or the currently received read address stored in the register in order to perform a read operation in the single-port memory in response to the start or stop of a write operation in any cycle.
  18. The method according to claim 11, further comprising configuring the single-port memory to function as one of 1R/xW, yR/xW, yR/1W, xW, or yR multi-port memory by selectively using a subset of a plurality of read buffers and a plurality of write buffers in a first time, wherein x and y are integer values of 2 or more.
  19. The method according to claim 18, further comprising reconfiguring the single-port memory to function as a different multi-port memory by selectively using different subsets of the plurality of read and write buffers during a second time after the first time.
  20. A multi-port memory system, A single-port memory capable of performing only one read or one write operation at a time, wherein the depth of the multi-port memory system is greater than the depth of the single-port memory, and the width of the multi-port memory system is smaller than the width of the single-port memory, A first register, coupled to the write data port of the single-port memory and configured to store the write data word received when the single-port memory is performing a read operation, The system comprises a second register, which is coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during the read operation, A multiport memory system in which the access pattern corresponding to the multiport system is sequential such that the memory addresses used to perform read and write operations increment according to a fixed amount.

Description

The examples in this disclosure generally relate to multiport memory systems (e.g., systems capable of performing multiple reads and writes in parallel) using single-port memory (e.g., memory elements capable of performing read-only or write-only operations at any given time). Many applications require memory that can perform read and write operations in parallel (e.g., multi-port memory systems). These systems typically include dual-port memory (i.e., memory that can perform at least one read and write operation in parallel) to implement large delay buffers and dynamic coefficient storage. In application-specific integrated circuits (ASICs), dual-port memory consumes more area and power per bit than single-port memory (i.e., memory that can perform only one read or one write operation at any given time). Also, multiple independent small memories are inefficient in terms of area compared to a single large memory. Therefore, replacing multi-port memory (e.g., two-port memory that can perform read and write operations in parallel) with single-port memory offers significant area and power advantages. Doing so can reduce the area of the memory macro by 40%. One embodiment describes a multiport memory system comprising: a single-port memory capable of performing only one read or one write operation at a time, wherein the address space of the single-port memory is less than or equal to half the address space of the multiport memory system; a divider configured to divide the received read address and the write address; a first register coupled to the write data port of the single-port memory and configured to store the write data word received while the single-port memory is performing a read operation; and a second register coupled to the read data port of the single-port memory and configured to store the first data word among a plurality of data words read from the single-port memory during a read operation. Furthermore, from the perspective of an external entity, the multiport memory system performs at least one of the following: (i) performing at least one read and at least one write operation in parallel, or (ii) performing multiple reads or multiple writes in parallel using the single-port memory. Another embodiment described herein is a method comprising: writing a first plurality of data words to a single-port memory using a write data port during a first cycle; reading a second plurality of data words from a first memory address of the single-port memory using a read data port during a second cycle; storing the first data word of the second plurality of data words in a first register coupled to the read data port during a second cycle; outputting the second data word of the second plurality of data words as read data during a second cycle; storing the first received word in a second register coupled to the write data port of the single-port memory during a second cycle; writing the first received word and the second received word to a second memory address of the single-port memory using a write data port during a third cycle; and outputting the second data word of the second plurality of data words as read data during a third cycle. Another embodiment described herein is a multiport memory system comprising: a single-port memory capable of performing only one read or one write operation at a time, wherein the depth of the multiport memory system is greater than the depth of the single-port memory, and the width of the multiport memory system is less than the width of the single-port memory; a first register coupled to the write data port of the single-port memory and configured to store a write data word received while the single-port memory is performing a read operation; and a second register coupled to the read data port of the single-port memory and configured to store a first data word among a plurality of data words read from the single-port memory during a read operation. Furthermore, the access pattern corresponding to the multiport system is sequential such that the memory addresses used to perform read and write operations increment according to a fixed amount. To ensure a detailed understanding of the above features, a more specific explanation, concisely summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting. This is a diagram illustrating a multiport memory system implemented using single-port memory, as an example.This is a timing diagram illustrating an example of performing parallel read and write operations using a single-port memory.This is a diagram illustrating a multiport memory system implemented using single-port memory, as an example.This is a diagram illustrating a 1W3R memory system implemented using a single-port memory, as an example.This is a diagram illustrat