JP-2026076288-A - Semiconductor equipment

Abstract

[Problem] To reduce the warping of the semiconductor substrate while shortening the length of the gate trench. [Solution] The semiconductor device (400) comprises a semiconductor layer (14) formed on a semiconductor substrate (12), a plurality of sets of gate trenches formed in the semiconductor layer (14), including a first set (S1) and a second set (S2), a plurality of gate electrodes, and gate wiring (52) electrically connected to the plurality of gate electrodes. Each of the gate trenches in the first set (S1) extends along a first direction in a plan view. Each of the gate trenches in the second set (S2) extends along a second direction perpendicular to the first direction in a plan view. The semiconductor device (400) further comprises a first communicating trench (402) extending along a second direction in a plan view, which connects the first set of gate trenches (S1) to each other at their ends, and a second communicating trench (404) extending along a first direction in a plan view, which connects the second set of gate trenches (S2) to each other at their ends. [Selection Diagram] Figure 7

Inventors

• 三田 翔也

Assignees

• ローム株式会社

Dates

Publication Date

20260511

Application Date

20260206

Priority Date

20210322

Claims (15)

1. A semiconductor device, Semiconductor substrate and A semiconductor layer formed on the semiconductor substrate, including an outer peripheral region and an active region surrounded by the outer peripheral region in a plan view, Multiple sets of gate trenches, including a first set and a second set, are formed in the semiconductor layer. Multiple gate electrodes, each embedded in a corresponding gate trench among the multiple sets of gate trenches, An insulating layer formed on the semiconductor layer, A gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes, The system comprises a source wiring formed on the insulating layer and spaced apart from the gate wiring, Each of the first set of gate trenches extends along a first direction in a plan view, Each of the second set of gate trenches extends along a second direction perpendicular to the first direction in a plan view, The aforementioned semiconductor device is A first connecting trench extending along the second direction in a plan view, which connects the first set of gate trenches to each other at their ends, The invention further comprises a second connecting trench extending along the first direction in a plan view, which connects the second set of gate trenches to each other at their ends, Semiconductor equipment.
2. The gate wiring includes an outer gate wiring section arranged in the outer peripheral region in a plan view, and an inner gate wiring section arranged in the active region in a plan view. The outer peripheral gate wiring portion includes a first gate finger that extends along the first direction in a plan view, The inner gate wiring portion includes a second gate finger that extends along the second direction in a plan view, Each of the first set of gate trenches includes two ends, and in plan view intersects the second gate finger between the two ends, Each of the second set of gate trenches includes two ends, and in plan view, intersects the first gate finger between the two ends. The semiconductor device according to claim 1.
3. The aforementioned source wiring is The outer peripheral source wiring section arranged in the outer peripheral region, The semiconductor device according to claim 2, further comprising an internal source wiring portion arranged in the active region.
4. Each of the first set of gate trenches is entirely located within the active area. The semiconductor device according to claim 3, wherein each of the second set of gate trenches is arranged to span the active region and the outer peripheral region.
5. Each gate electrode embedded in the first set of gate trenches is electrically connected to the second gate finger in the region where each set of gate trenches intersects with the second gate finger in a plan view. The semiconductor device according to any one of claims 2 to 4, wherein the gate electrodes embedded in each of the second set of gate trenches are electrically connected to the first gate finger in the region where each of the second set of gate trenches and the first gate finger intersect in a plan view.
6. The semiconductor device according to any one of claims 2 to 5, wherein the second gate finger intersects, in a plan view, with two or more sets of gate trenches, including the first set of gate trenches.
7. The semiconductor device according to any one of claims 2 to 6, wherein the inner gate wiring portion further includes at least one other gate finger that intersects the second gate finger in a plan view.
8. The semiconductor device according to claim 7, wherein the at least one additional gate finger includes one gate finger extending in the first direction in a plan view.
9. The semiconductor device according to claim 7, wherein the at least one additional gate finger includes two gate fingers extending in the first direction in a plan view.
10. The semiconductor device according to any one of claims 2 to 9, wherein the inner gate wiring portion further includes a third gate finger that forms a T-shaped joint with the second gate finger in a plan view.
11. The semiconductor device according to any one of claims 2 to 10, wherein the outer peripheral gate wiring portion further includes a fourth gate finger extending along the second direction in a plan view.
12. The semiconductor device according to any one of claims 1 to 11, wherein each set of gate trenches comprises a plurality of gate trenches arranged at equal intervals and parallel to one another.
13. The semiconductor substrate includes a surface on which the semiconductor layer is formed, and the surface includes a first edge extending along the first direction and a second edge extending along the second direction. Each of the first set of gate trenches has a length of 1/2 or less of the dimension of the first side, Each of the second set of gate trenches has a length of no more than half the dimension of the second side. A semiconductor device according to any one of claims 1 to 12.
14. The semiconductor device according to claim 13, wherein each of the first set of gate trenches has a length of 1/3 or less of the dimension of the first side.
15. The semiconductor device according to any one of claims 1 to 14, wherein the first connecting trench and the second connecting trench are arranged adjacent to each other at right angles.

Description

This disclosure relates to semiconductor devices. Patent Document 1 discloses a semiconductor device equipped with a metal-insulator-semiconductor field-effect transistor (MISFET) having a trench gate structure. In the semiconductor device of Patent Document 1, gate electrodes embedded in each of the multiple gate trenches are electrically connected to gate wiring (gate fingers) via gate contacts. Japanese Patent Publication No. 2020-202313 [overview] In a MISFET having a trench gate structure, the shorter the length of the gate trench, the lower the resistance of the electrode (e.g., gate electrode) embedded in the gate trench. Using a gate finger as described in Patent Document 1 makes it possible to make the length of the gate trench placed in the chip relatively short. However, an arrangement in which each of the multiple gate trenches extends along the same direction in a plan view has the problem that the warping of the semiconductor substrate (wafer) on which the MISFET is formed becomes relatively large during the process. A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate and including an outer peripheral region and an active region surrounded by the outer peripheral region in a plan view, a plurality of gate trenches formed in the semiconductor layer, including a first set and a second set, a plurality of gate electrodes, each embedded in a corresponding gate trench of the plurality of gate trenches, an insulating layer formed on the semiconductor layer, gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes, and source wiring formed on the insulating layer and spaced apart from the gate wiring. Each of the first set of gate trenches extends along a first direction in a plan view. Each of the second set of gate trenches extends along a second direction perpendicular to the first direction in a plan view. The semiconductor device further comprises a first communicating trench extending along the second direction in a plan view, which connects the first set of gate trenches at their ends, and a second communicating trench extending along the first direction in a plan view, which connects the second set of gate trenches at their ends. Figure 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment.Figure 2 is a schematic cross-sectional view of the semiconductor device along the line F2-F2 in Figure 1.Figure 3 is a schematic cross-sectional view of the semiconductor device along the line F3-F3 in Figure 1.Figure 4 is a schematic plan view of an exemplary semiconductor device relating to the first modification example.Figure 5 is a schematic plan view of an exemplary semiconductor device relating to the second modification example.Figure 6 is a schematic plan view of an exemplary semiconductor device according to the third modification example.Figure 7 is a schematic plan view of an exemplary semiconductor device relating to the fourth modification example. [Detailed explanation] Some embodiments of the semiconductor device of this disclosure will be described below with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting this disclosure. The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of this disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of this disclosure or the application and use of such embodiments. Figure 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment. In this disclosure, the term "plan view" refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in Figure 1. The semiconductor device 10 is, for example, a MISFET having a trench gate structure. The semiconductor device 10 includes a semiconductor substrate 12, a semiconductor layer 14 formed on the semiconductor substrate 12, a plurality of gate trenches S1, S2 formed in the semiconductor layer 14, and an insulating layer 16 formed on the semiconductor layer 14. In this embodiment, the semiconductor substrate 12 may be a Si substrate. The semiconductor substrate 12 includes a bottom surface 12A (described later with reference to Figure 2) and an upper surface 12B opposite to the bottom surface 12A. In Figure 1, the Z direction is perpendicular to the bottom surface 12A and the upper surface 12B of the semiconductor substrate 12. In the example shown in Figure 1, the top surface 12B of the semi