JP-2026076300-A - Full nanosheet air gap spacer

Abstract

[Problem] To provide a nanosheet transistor that reduces parasitic capacitance. [Solution] The nanosheet transistor includes a spacer region 156 between a high-k metal gate stack 142 and an epitaxial layer 136. The spacer region includes a first nanosheet stack having a plurality of nanosheets 102. The spacer region includes an internal spacer region 158 positioned between nanosheets, and a lateral subway region 160 located along the edges of a nanosheet, the internal spacer region, and another nanosheet. [Selection Diagram] Figure 15

Inventors

• チャン、ジンギュン
• シエ、ルイロン
• ヴェガ、レイナルド
• チョン、カングオ
• ユ、ラン

Assignees

• インターナショナル・ビジネス・マシーンズ・コーポレーション

Dates

Publication Date

20260511

Application Date

20260209

Priority Date

20210625

Claims (7)

1. A method for manufacturing a nanosheet transistor, comprising forming a nanosheet stack comprising a sacrificial internal spacer and a nanosheet, and forming an epitaxial layer adjacent to the nanosheet stack, The epitaxial layer is recessed to expose the sacrificial internal spacer at the corner etch portion, and the sacrificial internal spacer is removed to form an air gap around the nanosheet. Methods that include...
2. The interlayer dielectric layer is penetrated to open the contact cut, the spacer within the contact cut is etched, and the epitaxial layer is exposed. The method according to claim 1, including the method described in claim 1.
3. The method according to claim 1, comprising forming a spacer between the nanosheet stack and the substrate.
4. The method according to claim 1, wherein the air gap includes a lateral subway region along the edge of the nanosheet.
5. The method according to claim 1, comprising filling the corner etched portion with a non-conformal dielectric deposit.
6. The method according to claim 5, comprising forming trench contacts around the non-conformal dielectric deposit.
7. The method according to claim 1, wherein removing the sacrificial internal spacer includes etching the sacrificial internal spacer through the corner etch portion.

Description

This invention generally relates to the field of semiconductor device manufacturing, and more particularly to the fabrication of nanosheet transistors having stacked air gaps between stacked sheets and lateral subway air gaps along the edges. As semiconductor microchips and integrated circuits become smaller, vertically stacked semiconductor nanosheets are increasingly being used. Nanosheets are two-dimensional nanostructures whose vertical thickness is substantially smaller than their width. Semiconductor nanosheets are considered a viable option for reducing the size of semiconductor devices. By vertically stacking semiconductor nanosheets, area efficiency can be improved, and the drive current can be increased within a given layout. A typical process flow for semiconductor nanosheet formation involves the formation of a material stack containing a silicon-germanium sacrificial layer between silicon nanosheets. After removing the sacrificial layer, vertically stacked, suspended silicon nanosheets are obtained. Functional gate structures can be formed above and below each silicon nanosheet. One embodiment of the present invention includes a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack having a first nanosheet and a second nanosheet. The spacer region may include an internal spacer region positioned between the first and second nanosheets, and lateral subway regions located along the edges of the first nanosheet, the internal spacer region, and the second nanosheet. One embodiment of the present invention includes a method for manufacturing a nanosheet transistor. This method may include forming a nanosheet stack containing sacrificial internal spacers and nanosheets; forming an epitaxial layer adjacent to the nanosheet stack; recessing the epitaxial layer to expose the sacrificial internal spacers at the corner etched areas; and removing the sacrificial internal spacers to form an air gap around the nanosheets. One embodiment of the present invention includes a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack comprising a first nanosheet and a second nanosheet, and an internal spacer region between the first and second nanosheets. The internal spacer region may include an air gap across the widths of the first and second nanosheets. This figure shows a nanosheet transistor in the manufacturing stage of a processing method according to one embodiment of the present invention.Figure 1 is a cross-sectional side view of a nanosheet transistor, where similar reference numbers refer to similar features in subsequent manufacturing stages of the processing method.Figure 1 is a cross-sectional side view of a nanosheet transistor, where similar reference numbers in the previous figure refer to similar features in subsequent manufacturing stages of the processing method.Figure 7 is a schematic top view of a nanosheet transistor during the manufacturing process, where similar reference numbers in the previous figure refer to the same features.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where the same reference numbers as in the previous figure refer to the same features and represent the manufacturing stage of the processing method that follows the previous figure.Figure 4 shows four cross-