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JP-2026076314-A - Information processing system, information processing device, server device, program, reconfigurable device, or method

JP2026076314AJP 2026076314 AJP2026076314 AJP 2026076314AJP-2026076314-A

Abstract

[Problem] To provide a system, information processing device, server device, reconfigurable device, program, cloud, and/or method for more appropriately utilizing reconfigurable devices. [Solution] The method includes 501 acquiring first resource information, which is information about hardware resources to be used when one or more bitstreams relating to a first computing node are written to a reconfigurable device, and second resource information, which is information about hardware resources to be used when one or more bitstreams relating to a second computing node are written to a reconfigurable device, and 504 generating composite resource information, which is information about hardware resources to be used when one or more bitstreams based on the first computing node and the second computing node are written to a reconfigurable device, using the first resource information and the second resource information. [Selection Diagram] Figure 5

Inventors

  • 福田 エリック 駿

Assignees

  • Ｃｈｉｐｔｉｐ Ｔｅｃｈｎｏｌｏｇｙ株式会社

Dates

Publication Date
20260511
Application Date
20260213

Claims (15)

  1. First resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the first computing node are written to a reconfigurable device, Second resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the second computing node are written to a reconfigurable device, The acquisition unit acquires the following: A generation unit generates composite resource information, which is information about hardware resources that can be used when one or more bitstreams based on the first computing node and the second computing node are written to a reconfigurable device, using the first resource information and the second resource information. A system equipped with these features.
  2. The first resource information includes the number of first logic blocks, The second resource information includes the second logic block count, The generation unit calculates the total number of logic blocks by adding the number of first logic blocks and the number of second logic blocks, and generates the composite resource information including the total number of logic blocks. The system according to claim 1.
  3. The first resource information includes first frequency information, The second resource information includes the second frequency information, The generation unit generates the composite resource information which includes the smaller frequency of the first frequency information and the second frequency information, or both frequencies. The system according to claim 1 or 2.
  4. The generation unit generates the composite resource information based on the input/output relationship between the first computing node and the second computing node. The system according to any one of claims 1 to 3.
  5. It further includes an identification unit that identifies a hardware resource capable of executing the compute node corresponding to the aforementioned composite resource information, The system according to any one of claims 1 to 4.
  6. The identification unit includes a determination unit that compares at least one attribute in the composite resource information with an attribute corresponding to the at least one attribute in the resource information relating to the one hardware resource, and determines that the latter can perform the former. The system according to claim 5.
  7. The identification unit identifies the hardware resource using usage information based on at least one attribute in the composite resource information and an attribute corresponding to the at least one attribute in the resource information relating to the hardware resource. The system according to claim 5.
  8. A selection unit selects a subset of the first computing node group, which includes the first and second computing nodes, from a first computing node group consisting of a plurality of computing nodes including the first and second computing nodes, using information relating to input/output paths between at least some of the computing nodes in the first computing node group. The system according to any one of claims 1 to 7, comprising:
  9. A selection unit selects a subset of the first group of computing nodes, which includes the first and second computing nodes, from a first group of computing nodes comprising a plurality of computing nodes including the first and second computing nodes, using resource information of a reconfigurable device or resource information of a PR region within the reconfigurable device. The system according to any one of claims 1 to 8, comprising:
  10. One or more information processing devices, First resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the first computing node are written to a reconfigurable device, Second resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the second computing node are written to a reconfigurable device, means of obtaining, A generation means that generates composite resource information, which is information about hardware resources that can be used when one or more bitstreams based on the first computing node and the second computing node are written to a reconfigurable device, using the first resource information and the second resource information. A program to make it work as such.
  11. The information processing device includes a memory for storing the first resource information and/or the second resource information. The program according to claim 10.
  12. The information processing device includes a computing device that performs the generation process. The program according to claim 10 or 11.
  13. One or more information processing devices First resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the first computing node are written to a reconfigurable device, Second resource information, which is information about hardware resources that may be used when one or more bitstreams relating to the second computing node are written to a reconfigurable device, Acquisition step to obtain, A generation step of generating composite resource information, which is information about hardware resources that can be used when one or more bitstreams based on the first computing node and the second computing node are written to a reconfigurable device, using the first resource information and the second resource information. How to do it.
  14. The information processing device includes a memory for storing the first resource information and/or the second resource information. The method according to claim 13.
  15. The information processing device includes a computing device that performs the generation process. The method according to claim 13 or 14.

Description

The technologies disclosed in this application relate to systems, information processing devices, server devices, reconfigurable devices, programs, clouds, and/or methods. In recent years, reconfigurable devices, which allow for circuit modification, have begun to be introduced in various fields. Japanese Patent Publication No. 2020-135318Japanese Patent Publication No. 2010-251925Japanese Patent Publication No. H7-6080 Figure 1 is a block diagram illustrating an example of the relationship between a system according to one embodiment and a reconfigurable device.Figure 2 is a block diagram illustrating an example of the relationship between a system according to one embodiment and a reconfigurable device.Figure 3 shows an example of data used by a system according to one embodiment.Figure 4 shows an example of data used by a system according to one embodiment.Figure 5 shows an example of processing performed by a system according to one embodiment.Figure 6 shows an example data flow related to a system according to one embodiment.Figure 7 shows an example of processing performed by a system according to one embodiment.Figure 8 shows an example of processing performed by a system according to one embodiment.Figure 9 shows an example data flow related to a system according to one embodiment.Figure 10 shows an example of processing by a system according to one embodiment.Figure 11 shows an example of data used by a system according to one embodiment.Figure 12 shows a configuration related to a system according to one embodiment.Figure 13 shows an example of processing by a system according to one embodiment.Figure 14 shows an example of data used by a system according to one embodiment.Figure 15 is a diagram showing an example data flow related to a system according to one embodiment.Figure 16 shows a configuration related to a system according to one embodiment.Figure 17 is a block diagram showing an example configuration of a system according to one embodiment. 1. Introduction One example of the technology disclosed in this application relates to rewritable circuits. For example, the technology disclosed in this application includes technology relating to rewritable circuits themselves, technology utilizing non-rewritable circuits for rewritable circuits, and programs used in these circuits. One example of this technology may utilize an information processing device that includes non-rewritable circuits. Rewritable circuits are also called programmable logic devices, but in this application, they are collectively referred to as reconfigurable logic devices. On the other hand, non-rewritable circuits are sometimes called instruction decoding schemes, von Neumann type devices, etc., but in this application, they are collectively referred to as program variable devices. Examples of reconfigurable devices include PAL (Programmable Array Logic), PLA (Programmable Logic Array), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array), and CGRA (Coarse-Grained Reconfigurable Array). In the following sections of this application, while FPGAs may be used as an example of a reconfigurable device, it goes without saying that the provisions can also be applied to other reconfigurable devices. In particular, any reconfigurable device that possesses partial reconfiguration capabilities, that is, the ability to independently write to multiple regions (e.g., PR regions) within a single programmable logic device, may be capable of the region-specific processing described later. Here, "independently writable" may include the ability to write to other regions within the same programmable logic device while processing is being performed in one region of the same device. In this application, when we refer to "a single" reconfigurable device, it may be a physically independent device. Furthermore, a single reconfigurable device may structurally include one or more PR regions. A PR region may be a section whose circuit configuration can be independently modified. For each PR region, the reconfigurable device may perform one or more independent operations using partial reconfiguration, or it may perform one or more independent operations without using partial reconfiguration. Because they are independent, for example, if a single reconfigurable device includes PR region A and PR region B, PR region A and PR region B may operate independently in terms of circuit rewriting and circuit execution. Therefore, it may be possible to rewrite PR region B while PR region A is executing. Note that a reconfigurable device may also be referred to as a physical device, and a PR region may also be referred to as a virtual device. Furthermore, the data written to a reconfigurable device can be either a bitstream or a partial bitstream, but in the following explanation, both will be referred to simply as a bitstream. The bitstream in this application may be obtained by compiling a program (sometimes