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JP-2026076387-A - Semiconductor equipment

JP2026076387AJP 2026076387 AJP2026076387 AJP 2026076387AJP-2026076387-A

Abstract

[Problem] To suppress the peeling of the sealing resin from the connecting pad. [Solution] The semiconductor device 1 comprises a substrate 10 having a main surface, a semiconductor element having a main surface electrode facing the same direction as the main surface, connection pads 21, 31 spaced apart from the substrate 10 in a first direction X parallel to the main surface and having connection surfaces 24, 34 facing the same direction as the main surface, plating layers 71, 72 covering a portion of the connection surfaces 24, 34, wires 50, 60 with their first ends joined to the main surface electrode and their second ends 52, 62 joined to the connection pads 21, 31, and a sealing resin 80. The connection surfaces 24, 34 have covered portions 24a, 34a covered by the plating layers 71, 72 and exposed portions 24b, 34b exposed from the plating layers 71, 72. Viewed from the thickness direction perpendicular to the main surface, the covered portions 24a and 34a are located between the first portion of the exposed portions 24b and 34b and the second portion of the exposed portions 24b and 34b in the first direction X. [Selection Diagram] Figure 6

Inventors

  • 丹羽 大地
  • 齊藤 光俊

Assignees

  • ローム株式会社

Dates

Publication Date
20260511
Application Date
20260225
Priority Date
20200330

Claims (13)

  1. A substrate having a main surface, A semiconductor element mounted on the main surface and having main surface electrodes facing the same direction as the main surface, A connecting pad made of Cu, positioned spaced apart from the substrate in a first direction parallel to the main surface, and having a connecting surface facing the same direction as the main surface, A plating layer made of Ni, covering a part of the connection surface, A wire made of Al, with its first end joined to the main surface electrode and its second end joined to the plating layer, The semiconductor element, the connecting pad, the plating layer, and the sealing resin that seals the wire, Equipped with, The connecting surface has a covered portion that is covered by the plating layer and an exposed portion that is exposed from the plating layer. Viewed from the thickness direction perpendicular to the main surface, the covering portion is located between the first portion and the second portion of the exposed portion in the first direction. Semiconductor equipment.
  2. The main surface electrode includes a control electrode and a drive electrode. The connecting pad includes control pads and drive pads that are arranged spaced apart from the substrate in the first direction and spaced apart from each other along a second direction parallel to the main surface and perpendicular to the first direction. The wire includes a control wire connecting the control electrode and the control pad, and a drive wire connecting the drive electrode and the drive pad. The semiconductor device according to claim 1.
  3. The semiconductor device according to claim 2, wherein the wire diameter of the control wire is smaller than the wire diameter of the drive wire.
  4. The wire diameter of the control wire is 40 μm or more and 100 μm or less. The diameter of the drive wire is 200 μm or more and 600 μm or less. The semiconductor device according to claim 3.
  5. The joint portion of the control wire joined to the control pad is provided on the plating layer on the control pad, The joint portion of the drive wire joined to the drive pad is provided so as to protrude from the plating layer on the drive pad into the exposed portion of the connection surface of the drive pad. The semiconductor device according to claim 2.
  6. The semiconductor device according to claim 5, wherein the area of the portion of the drive wire joined to the upper surface of the plating layer is greater than or equal to the area of the drive wire's cross-section.
  7. The wire is joined to the connecting pad by ultrasonic bonding. The semiconductor device according to claim 1.
  8. The semiconductor element has a back electrode facing the opposite side from the main front electrode, The aforementioned substrate is made of Cu, The back electrode is connected to the substrate by solder. The semiconductor device according to claim 1.
  9. The semiconductor device according to claim 1, wherein the plating layer is a rough-surface plating layer whose surface is rougher than the connection surface of the connection pad.
  10. Viewed from the thickness direction, the covering portion is located between the third portion and the fourth portion of the exposed portion in a second direction parallel to the main surface and perpendicular to the first direction. The semiconductor device according to claim 1.
  11. Viewed from the thickness direction, the covered portion is surrounded by the exposed portion. The semiconductor device according to claim 10.
  12. The area of the covering portion of the control pad is smaller than the area of the covering portion of the drive pad. The semiconductor device according to claim 2.
  13. The joint portion of the drive wire joined to the drive pad has a first joint portion joined to the upper surface of the plating layer and a second joint portion joined to the exposed portion on the connection surface of the drive pad. The semiconductor device according to claim 5.

Description

This disclosure relates to semiconductor devices. The semiconductor device comprises a substrate, semiconductor elements such as power transistors mounted on the substrate, drive leads having drive pads connected to the source electrodes of the semiconductor elements via multiple drive wires, control leads having control pads connected to the gate electrodes of the semiconductor elements via control wires, and a sealing resin that encapsulates at least the semiconductor elements (see, for example, Patent Document 1). Japanese Patent Publication No. 2017-174951 [overview] It is required to suppress the peeling of the sealing resin from the connecting pad. A semiconductor device according to one aspect of this disclosure comprises a substrate having a main surface; a semiconductor element mounted on the main surface and having a main surface electrode oriented in the same direction as the main surface; a connection pad made of Cu, spaced apart from the substrate in a first direction parallel to the main surface, and having a connection surface oriented in the same direction as the main surface; a plating layer made of Ni covering a portion of the connection surface; a wire made of Al, with its first end joined to the main surface electrode and its second end joined to the plating layer; and a sealing resin sealing the semiconductor element, the connection pad, the plating layer, and the wire. The connection surface has a covered portion covered by the plating layer and an exposed portion exposed from the plating layer. Viewed from a thickness direction perpendicular to the main surface, the covered portion is located between a first portion and a second portion of the exposed portion in the first direction. Figure 1 is a schematic perspective view showing a semiconductor device of the first embodiment.Figure 2 is a schematic plan view of the semiconductor device according to the first embodiment.Figure 3 is a schematic rear view of the semiconductor device according to the first embodiment.Figure 4 is a cross-sectional view taken along line 4-4 in Figure 2.Figure 5 is a schematic side view of the semiconductor device according to the first embodiment.Figure 6 is a partially enlarged plan view showing a semiconductor device of the first embodiment.Figure 7 is a partially enlarged plan view showing a modified semiconductor device of the first embodiment.Figure 8 is a partially enlarged plan view showing a modified semiconductor device of the first embodiment.Figure 9 is a schematic perspective view showing a semiconductor device of the second embodiment.Figure 10 is a schematic plan view of the semiconductor device according to the second embodiment.Figure 11 is a schematic rear view of the semiconductor device according to the second embodiment.Figure 12 is a cross-sectional view taken along line 12-12 of Figure 10.Figure 13 is a schematic side view of a semiconductor device according to the second embodiment.Figure 14 is a schematic side view of a semiconductor device according to the second embodiment.Figure 15 is a cross-sectional photograph showing the drive pad and sealing resin. [Detailed explanation] The embodiments of the semiconductor device will be described below with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to those described below. Various modifications can be made to the embodiments below. (First Embodiment) A semiconductor device of the first embodiment will be described with reference to Figures 1 to 6. As shown in Figure 1, the semiconductor device 1 comprises a substrate 10, a drive lead 20, a control lead 30, a semiconductor element 40, a drive wire 50, a control wire 60, and a sealing resin 80. The sealing resin 80 seals the semiconductor element 40, the control wire 60, and the drive wire 50. The sealing resin 80 is formed so that parts of the substrate 10, the drive lead 20, and the control lead 30 are exposed. The drive lead 20 has an outer lead 20A protruding from the sealing resin 80, and an inner lead 20B provided within the sealing resin 80 and electrically connected to the outer lead 20A. In this embodiment, the outer lead 20A and the inner lead 20B are a single integrated component. The control lead 30 has an outer lead 30A protruding from the sealing resin 80, and an inner lead 30B provided within the sealing resin 80 and electrically connected to the outer lead 30A. In this embodiment, the outer lead 30A and the inner lead 30B are a single integrated component. The semiconductor device 1 of this embodiment is a TO (Transistor Outline)-252 package as defined in the package outline standard (JEITA standard). Furthermore, the semiconductor device 1 is a so-called SIP (Single Inline Package) type, where the outer lead 20A of the drive lead 20 and the outer lead 30A of the control lead 30 e