JP-2026514196-A - Display driver circuit and display device

JP2026514196AJP 2026514196 AJP2026514196 AJP 2026514196AJP-2026514196-A

Abstract

This application provides a display drive circuit and a display device, the display drive circuit including a plurality of frequency division control lines and a plurality of gate drive circuits connected in cascade, the plurality of frequency division control lines transmitting frequency division control signals to the plurality of gate drive circuits, each gate drive circuit including a plurality of first output modules, the plurality of first output modules output a plurality of first gate control signals having a phase difference. [Selection Diagram] Figure 4

Inventors

ヂャン・ファンシー
グァン・イェンチン

Assignees

武漢華星光電半導体顕示技術有限公司

Dates

Publication Date: 20260507
Application Date: 20240423
Priority Date: 20240403

Claims (20)

The gate drive unit includes a plurality of frequency division control lines and a plurality of gate drive circuits connected in cascade, the plurality of frequency division control lines are arranged to transmit frequency division control signals to the plurality of gate drive circuits, and each of the gate drive circuits is A node control module is electrically connected to the first and second nodes of the gate drive circuit of the current stage and is arranged to control the signals transmitted to the first and second nodes based on the corresponding first clock signal and start signal. A first output module comprising a plurality of first output modules, each of which is electrically connected to a first node and a second node, and each first output module is arranged to output a first gate control signal based on a corresponding second clock signal, the frequency division control signal, and signals from the first node and the second node, The system includes the first node, the second node, and at least one first frequency division module electrically connected to at least one first output module, and arranged to control signal transmission between the first node and the corresponding first output module based on the frequency division control signal and the signal of the second node, Here, the multiple first output modules are arranged to output a plurality of first gate control signals having a phase difference. Display driver circuit.
Each gate drive circuit includes X first output modules, and the phase difference of the first clock signal corresponding to two adjacent stages of the gate drive circuit is XH, where X ≥ 2 and H is the unit time length. The display drive circuit according to claim 1.
The gate drive circuits of the multiple stages are electrically connected to Y clock lines, and the Y clock lines transmit the corresponding first clock signal and second clock signal to the gate drive circuits of the multiple stages, where Y = 2X. The display drive circuit according to claim 2.
The gate drive circuits of the multiple stages are electrically connected to multiple clock lines, and Z of the multiple clock lines transmit the corresponding first clock signal to the gate drive circuits of the multiple stages, and Y of the multiple clock lines transmit the corresponding second clock signal to the gate drive circuits of the multiple stages, where Z = 2 and Y = 2X. The display drive circuit according to claim 1.
Each gate drive circuit includes two first output modules, and the Y clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock line transmits the corresponding second clock signal to one of the first output modules in the gate drive circuit of the second k+1 stage, the second clock line transmits the corresponding second clock signal to the other first output module in the gate drive circuit of the second k+1 stage, the third clock line transmits the corresponding second clock signal to one of the first output modules in the gate drive circuit of the second k+2 stage, and the fourth clock line transmits the corresponding second clock signal to the other first output module in the gate drive circuit of the second k+2 stage, where k ≥ 0. A display drive circuit according to any one of claims 3 to 4.
The third clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+1 stage, and the first clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+2 stage. The display drive circuit according to claim 5.
The Z clock lines include a fifth clock line and a sixth clock line. Here, the fifth clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+1 stage, and the sixth clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+2 stage. The display drive circuit according to claim 5.
Each of the first output modules is: A first output transistor wherein the control terminal of the first output transistor is electrically connected to the corresponding first frequency division module, the input terminal of the first output transistor is arranged to receive the corresponding second clock signal, and the output terminal of the first output transistor is electrically connected to the first output terminal of the gate drive circuit of the current stage that outputs the first gate control signal, A second output transistor, wherein the control terminal of the second output transistor is electrically connected to the second node, the input terminal of the second output transistor is electrically connected to the first power supply terminal, and the output terminal of the first output transistor is electrically connected to the first output terminal, A first capacitor, the first terminal of which is electrically connected to the control terminal of the first output transistor, and the second terminal of which is electrically connected to the first output terminal, The display drive circuit according to claim 1.
At least one of the first output modules includes a first switching transistor, the control terminal of the first switching transistor being electrically connected to the second node of the gate drive circuit of the previous stage, the input terminal of the first switching transistor being electrically connected to the corresponding first frequency division module, and the output terminal of the first switching transistor being electrically connected to the control terminal of the first output transistor. The display drive circuit according to claim 8.
At least one of the gate drive circuits is A second switching transistor wherein the control terminal of the second switching transistor receives the corresponding first clock signal, and the input terminal of the second switching transistor is electrically connected to at least one input terminal of the first switching transistor, A third switching transistor, wherein the control terminal of the third switching transistor is electrically connected to the second node, the input terminal of the third switching transistor is electrically connected to the first power supply terminal, and the output terminal of the third switching transistor is electrically connected to the output terminal of the second switching transistor, The display drive circuit according to claim 9.
The multiple frequency division control lines include a first frequency division control line, and the first frequency division module is A first frequency division transistor, wherein the control terminal of the first frequency division transistor is electrically connected to the second node, A second frequency division transistor wherein the control terminal of the second frequency division transistor is electrically connected to the output terminal of the first frequency division transistor, the input terminal of the second frequency division transistor is electrically connected to the first node, and the output terminal of the second frequency division transistor is electrically connected to the corresponding first output module, A second capacitor, wherein the first terminal of the second capacitor is electrically connected to the control terminal of the second frequency division transistor, and the second terminal of the second capacitor is electrically connected to the output terminal of the second frequency division transistor, Here, the input terminals of the first frequency division transistors in the multiple gate drive circuits are electrically connected to the first frequency division control line. The display drive circuit according to claim 1.
At least one of the gate drive circuits is A second output module is electrically connected to the first node and is configured to output a corresponding frequency division control signal and a second gate control signal based on the signal of the first node, The first node, the second node, and the second output module are further comprising a second frequency division module electrically connected to the second output module and arranged to control signal transmission between the first node and the second output module based on the corresponding frequency division control signal and the signal of the second node, The display drive circuit according to claim 1.
The multiple frequency division control lines include a second frequency division control line, and the second frequency division module is A third frequency division transistor, wherein the control terminal of the third frequency division transistor is electrically connected to the second node, A fourth frequency division transistor, wherein the control terminal of the fourth frequency division transistor is electrically connected to the output terminal of the third frequency division transistor, the input terminal of the fourth frequency division transistor is electrically connected to the first node, and the output terminal of the fourth frequency division transistor is electrically connected to the corresponding second output module, A third capacitor, wherein the first terminal of the third capacitor is electrically connected to the control terminal of the fourth frequency division transistor, and the second terminal of the third capacitor is electrically connected to the output terminal of the fourth frequency division transistor, Here, the input terminals of the third frequency division transistors in the multiple gate drive circuits are electrically connected to the second frequency division control line. The display drive circuit according to claim 12.
The second output module is, A third output transistor wherein the control terminal of the third output transistor is electrically connected to the output terminal of the fourth frequency division transistor, the input terminal of the third output transistor is electrically connected to the second power supply terminal, and the output terminal of the third output transistor is electrically connected to the second output terminal of the gate drive circuit of the current stage that outputs the second gate control signal, A fourth output transistor, wherein the control terminal of the fourth output transistor is electrically connected to the first node, the input terminal of the fourth output transistor is electrically connected to the third power supply terminal, and the output terminal of the fourth output transistor is electrically connected to the second output terminal, The display drive circuit according to claim 13.
At least one of the gate drive circuits is A fourth switching transistor wherein the control terminal of the fourth switching transistor receives the corresponding first clock signal, and the input terminal of the fourth switching transistor is electrically connected to the input terminal of the third output transistor, A fifth switching transistor, wherein the control terminal of the fifth switching transistor is electrically connected to the second node, the input terminal of the fifth switching transistor is electrically connected to the first power supply terminal, and the output terminal of the fifth switching transistor is electrically connected to the output terminal of the fourth switching transistor, The display drive circuit according to claim 14.
The node control module is A first transistor wherein the control terminal of the first transistor is arranged to receive the corresponding start signal, and the input terminal of the first transistor is electrically connected to a third power supply terminal or a fourth power supply terminal. A second transistor wherein the control terminal of the second transistor is electrically connected to the first control terminal of the first transistor, the input terminal of the second transistor is electrically connected to the first power supply terminal, and the output terminal of the second transistor is electrically connected to the output terminal of the first transistor, A third transistor wherein the control terminal of the third transistor is arranged to receive the corresponding first clock signal, the input terminal of the third transistor is electrically connected to the output terminal of the first transistor, and the output terminal of the third transistor is electrically connected to the first node, A fourth transistor wherein the control terminal of the fourth transistor is electrically connected to the first node, the input terminal of the fourth transistor is electrically connected to the fourth power supply terminal, and the output terminal of the fourth transistor is electrically connected to the second node, A fifth transistor wherein the control terminal of the fifth transistor is electrically connected to the first node, the input terminal of the fifth transistor is electrically connected to the first power supply terminal, and the output terminal of the fifth transistor is electrically connected to the second node, A sixth transistor, wherein the control terminal of the sixth transistor is electrically connected to the second node, the input terminal of the sixth transistor is electrically connected to the third power supply terminal, and the output terminal of the sixth transistor is electrically connected to the first node, The display drive circuit according to claim 1.
The node control module is A seventh transistor wherein the control terminal of the seventh transistor is arranged to receive the corresponding first clock signal, and the output terminal of the seventh transistor is electrically connected to the first node, The eighth transistor includes an eighth transistor whose control terminal is electrically connected to the second node, whose input terminal is electrically connected to the first power supply terminal, and whose output terminal is electrically connected to the input terminal of the seventh transistor. The display drive circuit according to claim 16.
A display drive circuit according to any one of claims 1 to 17, A display panel is electrically connected to the display driving circuit and includes a plurality of subpixels, each subpixel including a light-emitting element, a driving transistor, and a data transistor, wherein the driving transistor is arranged to generate a driving current for driving the light-emitting element to emit light, and the data transistor is arranged to transmit a data signal to the control terminal of the driving transistor, Here, the multiple first output modules in the same gate drive circuit are electrically connected to the control terminals of the data transistors in multiple adjacent rows of subpixels, and each first gate control signal is electrically connected to the control terminal of the data transistor in at least one row of subpixels. Display device.
Each of the first output modules is electrically connected to the control terminal of the data transistor in one row of the subpixels, and each of the gate drive circuits includes two of the first output modules, and the two first output modules in the same gate drive circuit are electrically connected to the control terminals of the data transistors in two adjacent rows of the subpixels. The display device according to claim 18.
At least one of the subpixels includes a compensation transistor and a reset transistor, wherein the input terminal of the compensation transistor is electrically connected to the output terminal of the drive transistor, the output terminal of the compensation transistor is electrically connected to the control terminal of the drive transistor, the input terminal of the reset transistor is electrically connected to a reset line, and the output terminal of the reset transistor is electrically connected to the control terminal of the drive transistor. Here, each gate drive circuit outputs a second gate control signal to the control terminal of the compensation transistor or reset transistor in multiple subpixels in multiple adjacent rows. The display device according to claim 18.

Description

This application relates to the field of display technology, specifically to display driving circuits and display devices. This application claims priority to the Chinese patent application No. 202410405954.4, filed with the China Patent Office on April 3, 2024, and all contents of said application are incorporated herein by reference. By controlling the display panel to have different refresh rates corresponding to different display areas, region-division and frequency-division design can be realized, thereby reducing power consumption. However, the large number of transistors in the gate drive circuit used to realize region-division and frequency-division design in the display panel, and the gate drive unit containing gate drive circuits with multiple stages, occupy a relatively large bezel space on the display panel during layout design, making it disadvantageous for realizing a narrow bezel design for the display panel. This is a principle block diagram showing the display drive circuit provided by the embodiment of the present application. This is a principle block diagram showing a gate drive circuit provided by an embodiment of the present application. This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention.This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention.This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention.This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention.This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention. This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application.This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application.This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application.This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application.This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application. This is a schematic diagram showing a display device provided by an embodiment of the present application. This is a schematic diagram showing the configuration of a pixel driving circuit provided by an embodiment of the present invention. This is a timing diagram corresponding to the pixel driving circuit provided by the embodiment of the present application. This is a schematic diagram illustrating the display principle of high-frequency and low-frequency images provided by the embodiments of the present invention. To make the purpose, technical proposal, and effects of this application clearer and more evident, the application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely illustrative of the application and are not intended to limit it. This application provides a display drive circuit and a display device, the display drive circuit including a plurality of frequency division control lines and a plurality of gate drive circuits connected in cascade, the plurality of frequency division control lines transmitting frequency division control signals to the plurality of gate drive circuits, each gate drive circuit including a node control module, a plurality of first output modules and at least one first frequency division module, the node control module controlling signals transmitted to the first and second nodes of the gate drive circuit of the current stage based on a corresponding first clock signal and a start signal, the first frequency division module controlling signal transmission between the first node and at least one first output module based on a frequency division control signal and the signal of the second node, each first output module outputting a first gate control signal based on a corresponding second clock signal, a frequency division control signal, and the signals of the first and second nodes, and the plurality of first output modules output a plurality of first gate control signals having a phase difference. By arranging each gate drive circuit to simultaneously include multiple first output modules, and having these multiple first output modules output multiple first