JP-2026514197-A - display device

JP2026514197AJP 2026514197 AJP2026514197 AJP 2026514197AJP-2026514197-A

Abstract

The present invention provides a display device in which the control terminals of compensation transistors in a plurality of subpixels are electrically connected to the first output terminals of first gate drive circuits of a plurality of stages, the control terminals of reset transistors in a plurality of subpixels are electrically connected to the first output terminals of second gate drive circuits of a plurality of stages, and in the same subpixel, the frequency of the second gate control signal received by the reset transistor and the frequency of the first gate control signal received by the compensation transistor are the same. [Selection Diagram] Figure 1A

Inventors

ヂャン・ファンシー

Assignees

武漢華星光電半導体顕示技術有限公司

Dates

Publication Date: 20260507
Application Date: 20240423
Priority Date: 20240403

Claims (18)

A display panel comprising a plurality of subpixels, at least one of which comprises a light-emitting element, a drive transistor, a compensation transistor, and a reset transistor, wherein the drive transistor is arranged to generate a drive current to drive the light-emitting element to emit light, the output terminal of the reset transistor and the output terminal of the compensation transistor are electrically connected to the control terminal of the drive transistor, the input terminal of the compensation transistor is electrically connected to the output terminal of the drive transistor, and the input terminal of the reset transistor is arranged to receive a reset signal. The gate drive module includes a plurality of frequency division control lines electrically connected to the display panel and transmitting frequency division control signals, a first gate drive unit, and a second gate drive unit, wherein the plurality of frequency division control signals include a first frequency division control signal and a second frequency division control signal, the first gate drive unit includes a plurality of first gate drive circuits cascaded together, the second gate drive unit includes a plurality of second gate drive circuits cascaded together, the first gate drive circuit is arranged to control the level of the generated first gate control signal based on the first frequency division control signal, and the second gate drive circuit is arranged to control the level of the generated second gate control signal based on the second frequency division control signal. Here, both the first gate drive circuit and the second gate drive circuit include a first output terminal, the control terminals of the compensation transistors in a plurality of subpixels are electrically connected to the first output terminals of the first gate drive circuits in a plurality of stages to receive a plurality of first gate control signals, the control terminals of the reset transistors in a plurality of subpixels are electrically connected to the first output terminals of the second gate drive circuits in a plurality of stages to receive a plurality of second gate control signals, and in the same subpixel, the frequency of the second gate control signal received by the reset transistor and the frequency of the first gate control signal received by the compensation transistor are the same. Display device.
At least one of the subpixels includes a data transistor, the input terminal of the data transistor is arranged to receive a data signal, and the output terminal of the data transistor is electrically connected to the input terminal of the drive transistor. Both the first gate drive circuit and the second gate drive circuit include a second output terminal, the second output terminal of the first gate drive circuit outputs a third gate control signal, and the second output terminal of the second gate drive circuit outputs a fourth gate control signal. Here, the control terminals of the data transistors in the plurality of subpixels are electrically connected to the second output terminals of the plurality of first gate drive circuits and/or the second output terminals of the plurality of second gate drive circuits. The display device according to claim 1.
Within one display cycle, within at least one frame from the first frame onward, the frequency of the first gate control signal output from at least one of the first gate drive circuits is greater than or less than the frequency of the third gate control signal. The display device according to claim 2.
In one display cycle, within at least one frame from the first frame onward, the frequency of the second gate control signal output from at least one of the second gate drive circuits is less than or greater than the frequency of the fourth gate control signal. The display device according to claim 2.
The plurality of frequency division control lines include a first frequency division control line that transmits the first frequency division control signal and a second frequency division control line that transmits the second frequency division control signal, and both the first gate drive circuit and the second gate drive circuit are, A node control module is electrically connected to the first node and is arranged to control the signals of the first node based on a corresponding start signal and a first clock signal. A first frequency division control module is electrically connected to the first node, the second node, and the third node, and is arranged to control signal transmission between the first node and the second node based on the signal of the third node and the corresponding frequency division control signal. The system includes the first node, the second node, the first output terminal, and a first output module which is electrically connected and arranged to control a gate control signal output from the first output terminal based on signals from the first node and the second node, Here, the first frequency division control module in the first gate drive circuit of multiple stages is electrically connected to the first frequency division control line, and the first frequency division control module in the second gate drive circuit of multiple stages is electrically connected to the second frequency division control line. The display device according to claim 2.
At least one of the first gate drive circuit and the second gate drive circuit is A third node, a fourth node, and a second output module electrically connected to the second output terminal, and arranged to control the gate control signal output from the second output terminal based on the signals of the third node and the fourth node, and the corresponding second clock signal, A second frequency division control module is electrically connected to the node control module by the first and third nodes, electrically connected to the corresponding second output module by the fourth node, and is configured to control signal transmission between the first and fourth nodes based on the corresponding frequency division control signals. The display device according to claim 5.
The first gate drive circuit and the second gate drive circuit each include X second output modules and X second output terminals, and each second output module is electrically connected to one second output terminal. Here, the phase difference of the first clock signals corresponding to the first gate drive circuits of two adjacent stages is XH, the phase difference of the first clock signals corresponding to the second gate drive circuits of two adjacent stages is XH, X ≥ 1, and H represents the unit time length. The display device according to claim 6.
X > 1, and X second output modules in the same first gate drive circuit are arranged to output a plurality of third gate control signals having a phase difference, and X second output modules in the same second gate drive circuit are arranged to output a plurality of fourth gate control signals having a phase difference. The display device according to claim 7.
Each of the second output terminals is electrically connected to the control terminals of the data transistors in a plurality of subpixels in a row. The control terminals of the data transistors in the subpixels of rows L to L+X-1 are electrically connected in correspondence to the X second output terminals of the first gate drive circuit of the K stage and/or the X second output terminals of the second gate drive circuit of the K stage, where K≧1 and L=XK-(X-1). The display device according to claim 7.
X = 1, Here, the control terminal of the compensation transistor in the subpixel of the L row is electrically connected to the first output terminal of the first gate drive circuit of the K+1 stage, and the control terminal of the reset transistor in the subpixel of the L row is electrically connected to the first output terminal of the second gate drive circuit of the K-3 stage. The display device according to claim 7.
It further includes multiple clock lines, including a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock signal corresponding to the first gate drive circuit of the 4m+1 stage and the second gate drive circuit of the 4m+1 stage is a signal transmitted by the corresponding second clock line, the second clock signal corresponding to the first gate drive circuit of the 4m+1 stage and the second gate drive circuit of the 4m+1 stage is a signal transmitted by the corresponding first clock line, the first clock signal corresponding to the first gate drive circuit of the 4m+2 stage and the second gate drive circuit of the 4m+2 stage is a signal transmitted by the corresponding third clock line, and the second clock signal corresponding to the first gate drive circuit of the 4m+2 stage and the second gate drive circuit of the 4m+2 stage is a signal transmitted by the corresponding second clock line. The first clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+3 stage is a signal transmitted by the corresponding fourth clock line, the second clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+3 stage is a signal transmitted by the corresponding third clock line, the first clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+4 stage is a signal transmitted by the corresponding first clock line, and the second clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+4 stage is a signal transmitted by the corresponding fourth clock line. The display device according to claim 10.
X ≥ 2, Here, the control terminal of the compensation transistor in the subpixels of the L row to the L+X-1 row is electrically connected to the first output terminal of the first gate drive circuit of the K stage, and the control terminal of the reset transistor in the subpixels of the L row to the L+X-1 row is electrically connected to the first output terminal of the first gate drive circuit of the K-2 stage. The display device according to claim 7.
X = 2, and the display device further includes a plurality of clock lines, the plurality of clock lines including a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock line transmits the corresponding second clock signal to one second output module in the second k+1 stage first gate drive circuit and one second output module in the second k+1 stage second gate drive circuit, the second clock line transmits the corresponding second clock signal to another second output module in the second k+1 stage first gate drive circuit and another second output module in the second k+1 stage second gate drive circuit, the third clock line transmits the corresponding second clock signal to one second output module in the second k+2 stage first gate drive circuit and one second output module in the second k+2 stage second gate drive circuit, and the fourth clock line transmits the corresponding second clock signal to another second output module in the second k+2 stage first gate drive circuit and another second output module in the second k+2 stage second gate drive circuit, where k ≥ 0. The display device according to claim 12.
The third clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+1 stage and the second gate drive circuit of the 2k+1 stage, and the first clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+2 stage and the second gate drive circuit of the 2k+2 stage. The display device according to claim 13.
The plurality of frequency division control lines include a third frequency division control line and a fourth frequency division control line, and the first gate drive circuit and the second gate drive circuit each include one second frequency division control module. Here, the second frequency division control module in the first gate drive circuit of multiple stages is electrically connected to the third frequency division control line, and the second frequency division control module in the second gate drive circuit of multiple stages is electrically connected to the fourth frequency division control line. The display device according to claim 6.
The control terminals of the data transistors in multiple subpixels of the same row are electrically connected to the second output terminals of multiple first gate drive circuits and the second output terminals of multiple second gate drive circuits. Here, the third frequency division control line is electrically connected to the fourth frequency division control line. The display device according to claim 15.
In the first gate drive circuit of multiple stages, the start signal corresponding to the first gate drive circuit of the first stage has a change from an active level to an inactive level at a first time, and in the second gate drive circuit of multiple stages, the start signal corresponding to the second gate drive circuit of the first stage has a change from an active level to an inactive level at a first time. The display device according to claim 6.
The first gate drive circuit of the multiple stages is electrically connected to the control terminal of the compensation transistor in the multiple subpixels in a one-sided drive manner, and the second gate drive circuit of the multiple stages is electrically connected to the control terminal of the reset transistor in the multiple subpixels in a one-sided drive manner. The display device according to claim 1.

Description

This application relates to the field of display technology, and more specifically to a display device. This application claims priority to the Chinese patent application No. 202410404491.X filed with the China Patent Office on April 3, 2024, and all contents of said application are incorporated into this application by reference. In a pixel driving circuit, the compensation transistor and reset transistor, which are electrically connected to the control terminal of the driving transistor, are typically controlled using gate control signals output from gate driving circuits of different stages within the same gate driving unit. Furthermore, the reset transistor is turned on before the compensation transistor, thereby applying the reset signal to the control terminal of the driving transistor and achieving a potential reset relative to the control terminal. However, when a display panel displays using different display frequencies corresponding to different display areas, some sub-pixels corresponding to frequency-divided positions on the display panel may experience display abnormalities because the gate control signal used for the reset transistor is still at a high frequency when the gate control signal used for the compensation transistor is at a low frequency. This is a schematic diagram showing the configuration of the display device provided by the embodiment of the present application.This is a schematic diagram showing the configuration of the display device provided by the embodiment of the present application. This is a schematic diagram showing the configuration of subpixels provided by the embodiment of the present application.This is a schematic diagram showing the configuration of subpixels provided by the embodiment of the present application. This is a schematic diagram showing the connection between subpixels and gate drive modules provided by related technologies. This is a timing diagram corresponding to subpixels provided by related technologies.This is a timing diagram corresponding to subpixels provided by related technologies. This is a schematic diagram showing the configuration of the first gate drive unit and the second gate drive unit provided by the embodiment of the present application.This is a schematic diagram showing the configuration of the first gate drive unit and the second gate drive unit provided by the embodiment of the present application. This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention.This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention. This is a schematic diagram illustrating the display principle of high-frequency and low-frequency images provided by the embodiments of the present invention. This is a timing diagram of the first gate control signal and the second gate control signal provided by the embodiment of the present application.This is a timing diagram of the first gate control signal and the second gate control signal provided by the embodiment of the present application.This is a timing diagram of the first gate control signal and the second gate control signal provided by the embodiment of the present application.This is a timing diagram of the first gate control signal and the second gate control signal provided by the embodiment of the present application. This is a timing diagram of the write frame and hold frame corresponding to the subpixel provided by the embodiment of the present application. To make the purpose, technical proposal, and effects of this application clearer and more evident, the application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely illustrative of the application and are not intended to limit it. This application provides a display device in which a first gate drive unit includes a plurality of cascaded first gate drive circuits, a second gate drive unit includes a plurality of cascaded second gate drive circuits, the first gate drive circuits control the level of the generated first gate control signal based on a first frequency division control signal, the second gate drive circuits control the level of the generated second gate control signal based on a second frequency division control signal, the control terminals of the compensation transistors in a plurality of subpixels are electrically connected to the first output terminals that output the first gate control signal of the first gate drive circuits in a plurality of stages, and the control terminals of the reset transistors in a plurality of subpixels are electrically connected to the first output terminals that output the second gate control signal of the second gate drive circuits in a plurality of stages, thereby the reset transistors and compensation transistors are connected to the same gate d