JP-2026514219-A - Multi-threshold voltage integration scheme for semiconductor devices

Abstract

A method for manufacturing an electronic device is described. Embodiments of this disclosure advantageously provide a method for manufacturing an electronic device that reduces thickness, reduces leakage current, reduces thermal balance, and satisfies Vt requirements (including multi- Vt ), thereby improving the performance and reliability of the device. The method includes depositing an interface layer (e.g., silicon oxide (SiOx)) on the upper surface of a channel; depositing a hafnium-containing layer containing hafnium oxide (HfOx) and having a thickness of 5 Å or less on the interface layer; and depositing a dipole layer containing lanthanum nitride (LaN) on the hafnium-containing layer to form a p-type dipole stack and an n-type dipole stack on a semiconductor substrate. [Selection Diagram] Figure 1

Inventors

• ガンディコッタ， シュリーニヴァース
• マー， トンヂョウ
• バジャージ， ギーティカ
• チャタジー， デバディティヤ
• ユー， シン－ロン
• リン， ペイ シュアン
• ヤン， イーシオン

Assignees

• アプライド マテリアルズ インコーポレイテッド

Dates

Publication Date

20260507

Application Date

20240425

Priority Date

20230428

Claims (20)

1. In a method for manufacturing electronic devices, The method involves forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, wherein each of the p-type dipole stack and the n-type dipole stack is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate, and the formation of each of the p-type dipole stack and the n-type dipole stack is as follows: Depositing an interface layer on the upper surface of the channel, A method for manufacturing an electronic device, comprising depositing a hafnium-containing layer on the interface layer, wherein the hafnium-containing layer has a thickness of 5 Å or less, and depositing a dipole layer on the hafnium-containing layer, thereby forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate.
2. The method according to claim 1, wherein the interface layer includes a silicon oxide (SiOx) layer formed on doped or undoped silicon.
3. The method according to claim 1, wherein the hafnium-containing layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx).
4. The method according to claim 1, wherein the hafnium-containing layer has a thickness of 3 Å or less.
5. The method according to claim 1, wherein the deposition of the dipole layer includes exposing the semiconductor substrate to pulses of a metal-containing precursor and pulses of reactants by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.
6. The method according to claim 5, wherein the metal-containing precursor comprises one or more of the following: titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).
7. The method according to claim 5, wherein the reactant contains ammonia ( NH3 ).
8. The method according to claim 5, wherein the dipole layer comprises lanthanum nitride (LaN) or aluminum nitride (AlN).
9. The method according to claim 1, further comprising selectively etching a deposited dipole layer from one of the p-type dipole stacks or the n-type dipole stacks, and increasing the thickness of the dipole layer of the other of the p-type dipole stacks or the n-type dipole stacks to form an electronic device having multiple threshold voltages (multiple Vt ).
10. The method according to claim 1, further comprising depositing a high-dielectric-constant dielectric layer having a thickness in the range of 10 Å to 20 Å on the dipole layer.
11. The method according to claim 10, wherein the high dielectric constant dielectric layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
12. The method according to claim 10, further comprising annealing the p-type dipole stack and the n-type dipole stack at a temperature of 1000°C or less to drive metal atoms into the dipole layer, thereby increasing the density of the high-dielectric-constant dielectric layer and forming an annealed high-dielectric-constant dielectric layer.
13. The method according to claim 12, further comprising depositing a work function layer on the annealed high dielectric constant dielectric layer.
14. The method according to claim 1, which improves the threshold voltage ( Vt ) of the electronic device compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer.
15. The method according to claim 1, which reduces the leakage current (J g ) of the electronic device compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer.
16. In a method for manufacturing electronic devices, The method involves forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, wherein each of the p-type dipole stack and the n-type dipole stack is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate, and the formation of each of the p-type dipole stack and the n-type dipole stack is as follows: Depositing an interface layer on the upper surface of the channel, wherein the interface layer contains silicon oxide (SiOx). A method for manufacturing an electronic device, comprising depositing a hafnium-containing layer on the interface layer, wherein the hafnium-containing layer contains hafnium oxide (HfOx) and has a thickness of 5 Å or less, and depositing a dipole layer containing lanthanum nitride (LaN) on the hafnium-containing layer, thereby forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate.
17. The method according to claim 16, further comprising depositing a high dielectric constant dielectric layer on the dipole layer, wherein the high dielectric constant dielectric layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
18. The method according to claim 17, further comprising annealing the p-type dipole stack and the n-type dipole stack at a temperature of 1000°C or less to drive metal atoms into the dipole layer, thereby increasing the density of the high-dielectric-constant dielectric layer and forming an annealed high-dielectric-constant dielectric layer.
19. The method according to claim 18, further comprising depositing a work function layer on the annealed high dielectric constant dielectric layer.
20. The method according to claim 16, which reduces the leakage current (J g ) of the electronic device compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer.

Description

Embodiments of the present invention relate to the field of electronic device manufacturing, particularly to transistors. More specifically, embodiments of the present disclosure relate to FinFET devices and GAA devices, and methods for manufacturing said FinFET devices and GAA devices. Integrated circuits (INCS) have evolved into complex devices capable of containing millions of transistors, capacitors, and resistors on a single chip. In the course of INCS evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while form factor (i.e., the smallest component (or line) that can be produced using the manufacturing process) has decreased. A transistor is a component or element that is often formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate planar field-effect transistors (FETs), in which current flows through a semiconductor channel between the source and drain in response to a voltage applied to the control gate. As device dimensions shrink, maintaining switching speeds without failure becomes increasingly difficult due to the device's shape, dimensions, and materials. Several new technologies have emerged that allow chip designers to further reduce gate length. Controlling device structure dimensions remains a critical challenge for current and future generations of technology. Miniaturizing the materials currently used for negative-type metal oxide semiconductor (n-type MOS) transistors and positive-type metal oxide semiconductor (p-type MOS) transistors presents challenges due to changes in fundamental characteristics such as threshold voltage ( Vt ). Furthermore, transitioning transistor technology from planar FETs to FinFETs and then to GAA devices requires conformal work function layers that accommodate multiple threshold voltages (multiple Vt ). The adjustment range of Vt will likely be limited by changes in film thickness as the device size is further reduced. There are also challenges associated with conventional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven from a deposited film by spike annealing and then removed after being driven in. Spike annealing can cause a penalty to the equivalent oxide thickness (EOT) and a high heat balance because free oxygen atoms in the gate dielectric layer and upper dipole stack diffuse downward and oxidize the underlying silicon layer. In addition, precise control of the amount of dipole species in metal gate stacks, such as high-dielectric-constant metal gate stacks, is essential for achieving the desired Vt (or multi- Vt ) of the transistor. Conventional processes include "dipole-first" and "dipole-last" processes. Typically, a dipole-first process involves flowing a metal-containing precursor and reactant onto an interface layer to deposit metal atoms onto the interface layer (forming a treated interface layer) to achieve the desired dipole effect, followed by depositing a high-dielectric-constant dielectric layer on the treated interface layer. A dipole-last process typically involves forming an interface layer on a substrate, forming a high-dielectric-constant dielectric layer on the interface layer, flowing a metal-containing precursor and reactant onto the high-dielectric-constant dielectric layer to deposit metal atoms onto the high-dielectric-constant dielectric layer, and annealing the substrate to deliver metal atoms to the interface between the interface layer and the high-dielectric-constant dielectric layer to achieve the desired dipole effect. In the dipole rust process, instead of forming an extremely thin surface adsorption layer, an atomic layer deposition (ALD) process is performed to deposit a dipole layer with a thickness ranging from 3 Å to 20 Å, typically containing metal atoms in the form of oxides or nitrides. To prevent the regrowth of silicon oxide during the annealing process, a capping material is usually required on top of the dipole oxide/nitride layer. Conventional dipole-first processes allow for Vt adjustments exceeding approximately 200 millivolts (mV), while conventional dipole-last processes allow for Vt adjustments below approximately 200 mV. Therefore, conventional dipole-last processes would require multiple annealing steps to achieve high Vt levels similar to those achieved in conventional dipole-first processes. Switching to conventional dipole-first processes for higher Vt adjustability would result in the loss of multi- Vt capability, as no etching process is currently known that can selectively remove the dipole material without removing part of the silicon oxide (SiOx) interface layer. Furthermore, dipole-first processes also present challenges related to Vt shift and leakage current. Therefore, there is a need for