JP-2026514234-A - Non-conductive edge termination structure for semiconductor devices, and method for manufacturing the same.

Abstract

A method for forming an edge termination structure in a semiconductor device is provided. The method includes forming an epitaxial layer on a semiconductor substrate, wherein the epitaxial layer extends laterally across an active region and an edge termination region in the device; forming a plurality of active trenches in the active region and at least one outer trench in the edge termination region, wherein each of the outer trenches and the active trenches extends vertically through at least a portion of the epitaxial layer; at least partially filling each of the outer trenches and the active trenches with a first insulating material; forming a trench by etching a region of the epitaxial layer in the edge termination region adjacent to the last of the plurality of active trenches in the active region; and at least partially filling the trench with a second insulating material to form a trench structure as an edge termination structure in the semiconductor device. [Selection Diagram] Figure 1

Inventors

• ジャウレギ，デビッド
• ソロフィエフ，スタニスラフ
• ラッター，フィリップ

Assignees

• アイディアル セミコンダクター デバイス，インク．

Dates

Publication Date

20260507

Application Date

20240426

Priority Date

20230428

Claims (20)

1. A method for forming an edge termination structure in a semiconductor device, wherein the semiconductor device includes an active region where one or more active structures are formed, and an edge termination region where the edge termination structure is formed, the edge termination region being laterally adjacent to the active region, and the method is Forming an epitaxial layer on a semiconductor substrate, wherein the epitaxial layer extends laterally across the active region and the edge termination region; To form a plurality of active trenches within the active region and at least one outer trench in the edge termination region, wherein each of the outer trenches and the active trenches extends vertically through at least a portion of the epitaxial layer; Each of the outer trench and the active trench is filled at least partially with the first insulating material; Forming a trench by etching a region of the epitaxial layer in the edge termination region adjacent to the last trench of the plurality of active trenches in the active region; and, The method comprising filling the trench at least partially with a second insulating material to form a trench structure as a non-conductive edge termination structure in a semiconductor device.
2. The method described above is To form at least one boundary trench in the edge termination region, wherein the boundary trench extends vertically through at least a portion of the epiaxial layer and is spaced laterally from the at least one outer trench; and, The further step includes at least partially filling the at least one boundary trench with the first insulating material, Here, the trench structure is positioned between the outer trench and the boundary trench, and therefore a given side wall of the trench structure is defined by one of the outer trench and the boundary trench. The method according to claim 1.
3. The method according to claim 2, wherein the outer trench, the boundary trench, and the active trench are formed simultaneously using the same mask and in the same processing step.
4. The method according to claim 1, wherein the first width of at least one outer trench is greater than the second width of each of the plurality of active trenches.
5. The method according to claim 4, wherein the first width is at least twice the second width.
6. The method according to claim 2, wherein each of the at least one outer trench, the at least one boundary trench, and the plurality of active trenches is formed using a deep trench etching process having an aspect ratio greater than approximately 10:1.
7. The method according to claim 1, further comprising forming a first metal layer on at least the upper surface of the active region, wherein the first metal layer is configured to extend laterally above the at least one outer trench and above a portion of the trench structure in the edge termination region, and the extension of the first metal layer above the trench structure forms an electric field plate in the edge termination region.
8. The method according to claim 7, further comprising controlling the amount of extension of the first metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.
9. Forming a first metal layer at least on the upper surface of the active region; and, The method according to claim 1, further comprising forming a second metal layer on the upper surface of the first metal layer and extending laterally above the at least one outer trench and above a portion of the second insulating layer in the trench structure to form an electric field plate in the edge termination region.
10. The method according to claim 9, further comprising controlling the amount of extension of the second metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.
11. The method involves forming a first metal layer that is located at least on the upper surface of the active region and extends laterally above the at least one outer trench and a portion of the trench structure in the edge termination region, wherein the extension of the first metal layer above the trench structure forms a first electric field plate in the edge termination region; To form a second metal layer on the upper surface of the first metal layer and extending laterally above a portion of the second insulating layer in the trench structure, thereby forming a second electric field plate in the edge termination region; and, The method according to claim 1, further comprising controlling the amount of extension of at least one of the first metal layer and the second metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.
12. A first metal layer is formed on at least the upper surface of the active region to form a first inner electric field plate in the edge termination region, wherein a first portion of the first metal layer extends laterally from the active region above the at least one outer trench and above a portion of the trench structure; and, The method according to claim 2, further comprising forming a second portion of the first metal layer above the epitaxial layer, extending laterally above the at least one boundary trench and above a portion of the trench structure, thereby forming a first outer electric field plate in the edge termination region.
13. A first metal layer is formed on at least the upper surface of the active region to form a first outer electric field plate in the edge termination region, wherein a portion of the first metal layer extends laterally above the epitaxial layer, above the at least one boundary trench, and above a portion of the trench structure adjacent to the at least one outer trench; and, The method according to claim 2, further comprising forming a second metal layer that extends laterally above a portion of the second insulating layer in the trench structure, which is located on the upper surface of the first metal layer and adjacent to the at least one outer trench, thereby forming a secondary outer electric field plate in the edge termination region.
14. Forming a first metal layer at least on the upper surface of the active region; To form an inner electric field plate in the edge termination region by forming a first portion of a second metal layer that is located on the upper surface of the first metal layer and extends laterally above the at least one outer trench and a portion of the second insulating layer in the trench structure adjacent to the at least one outer trench; and, The method according to claim 2, further comprising forming a second portion of the second metal layer on the second insulating layer above the at least one boundary trench and a portion of the trench structure adjacent to the at least one boundary trench to form an outer electric field plate in the edge termination region.
15. The method according to claim 14, further comprising controlling the amount of extension of the first and second portions of the second metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.
16. The method according to claim 1, further comprising forming the at least one outer trench and the trench such that the depth of the at least one outer trench is greater than the depth of the trench in the edge termination region.
17. The method according to claim 1, further comprising controlling the width of the mesa region between the last of the plurality of active trenches in the active region and the outer trench in the edge termination region to adjust the difference in charge between the trench structure and the plurality of active trenches.
18. A semiconductor device comprising an active region and an edge termination region, wherein the edge termination region is laterally adjacent to the active region, and the semiconductor device is An epitaxial layer formed on a semiconductor substrate, wherein the epitaxial layer extends laterally across the active region and the edge termination region; A plurality of active trench structures formed within the active region and at least one active device, wherein each of the plurality of active trench structures extends vertically through at least a portion of the epitaxial layer and is at least partially filled with a first insulating material; At least one outer trench structure formed in the edge termination region, wherein the outer trench structure extends vertically through at least a portion of the epitaxial layer and is at least partially filled with the first insulating material, and the outer trench structure is adjacent to the last trench of the plurality of active trench structures in the active region; and, A trench structure extending vertically through at least a portion of the epitaxial layer in the edge termination region, wherein the trench structure has side walls defined by at least one outer trench structure, the trench structure is at least partially filled with a second insulating material, and the trench structure forms an edge termination structure in the semiconductor device configured to laterally isolate the active region from reverse voltage in the semiconductor device. The semiconductor device including the above.
19. The aforementioned semiconductor device is The present invention further includes at least one boundary trench structure formed in the edge termination region, The boundary trench structure extends vertically through at least a portion of the epitaxial layer and is at least partially filled with the first insulating material, and the boundary trench structure is spaced laterally from the at least one outer trench structure. Here, the trench structure is positioned between the outer trench structure and the boundary trench structure, and therefore a given side wall of the trench structure is defined by one of the outer trench structure and the boundary trench structure. The semiconductor device according to claim 18.
20. A first metal layer located on at least the upper surface of the plurality of active trench structures in the active region; A second metal layer on the second insulating layer extending over at least a portion of the trench structure, wherein the second metal layer forms an electric field plate for controlling the electric field distribution in the trench structure. The semiconductor device according to claim 18, further comprising the above.

Description

This application, referenced to a related application , claims priority under 35 U.S.SC. §119 to U.S. Provisional Application No. 63/498,962, “Non-conducting Edge Termination Structures for a Semiconductor Device and Methods of Fabricating the Same,” filed on 28 April 2023, and the disclosures of this application are incorporated by reference in their entirety for all purposes. This invention relates to semiconductor devices and methods for manufacturing the same, and more particularly to enhanced edge termination structures used in semiconductor devices, and methods for manufacturing such structures. Vertically conducting semiconductor devices within integrated circuits (ICs) have an active region enclosed by an edge termination region. In such vertical devices, primarily due to saw damage during device singulation or the lack of a blocking junction at the device's edge, the die edge always has the same or similar voltage potential as the device's bottom surface. Therefore, the edge termination region is a critical part of the device design to ensure lateral blocking of potential voltages between the active region and the die edge. While the active region must withstand vertical blocking voltage, the edge termination region must withstand blocking voltage in both the lateral and vertical directions. Because the edge termination region must maintain voltage blocking capability in both vertical and lateral directions, the design of the device's edge termination region is a critical factor in determining the device's performance and cost-effectiveness. Figure 1 is a schematic cross-sectional view illustrating at least a portion of an exemplary integrated circuit (IC) die according to one or more embodiments of the concept of the present invention.Figure 2 is a flowchart illustrating at least a portion of intermediate process steps in an exemplary method for manufacturing edge termination structures for use in semiconductor devices, according to one or more embodiments of the concept of the present invention.Figure 3A is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention.Figure 3B is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention.Figure 3C is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention.Figure 3D is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention.Figure 3E is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention.Figure 4A is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and/or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention.Figure 4B is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and/or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention.Figure 4C is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and/or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention.Figure 4D is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and/or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention.Figure 5 is a schematic cross-sectional view conceptually illustrating the charge balancing within a semiconductor device shown in Figure 4A, with the field plate removed, according to one or more embodiments of the present invention.Figure 6A is a schematic plan view illustrating at least a portion of the corner structure in a semiconductor device using a moat edge termination structure, and conceptually showing a method by which the capacitance of the moat structure at the corner can be determined.Figure 6B is a schematic plan view illustrating a